L2 Cache Placement on Memory Side of Crossbar
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Solution Overview
Problem
As the number of processors in multiprocessor systems increases, the complexity and access latency of cache snooping and access also increase, making it challenging to achieve increased parallelism without escalating complexity and latency.
Innovation Solution
Positioning L2 caches on the memory side of a routing crossbar allows processors to directly store messages in each other's caches, reducing inter-processor communication latency and enabling increased parallelism by adding processors and corresponding L2 caches, while each processor can access any cache line by determining the correct memory controller and issuing requests through the routing fabric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If L2 caches are directly coupled to each processor, then each processor can access other processors' caches with low latency, but the complexity and access latency increases as the number of processors increases
Solution Approach 1:
The patent segments the cache system by placing L2 caches on the memory side of the routing crossbar rather than directly coupled to processors. This segmentation allows the cache access function to be separated from processor coupling, enabling independent optimization of access paths and reducing snooping complexity as processor count increases.
Solution Approach 2:
The patent introduces a memory controller as an intermediary between processors and L2 caches. The memory controller manages cache access requests and coordinates snooping operations, reducing the direct complexity burden on each processor while maintaining low latency access through the routing crossbar fabric.
2Productivity
If processors are added to increase parallelism, then system processing throughput improves, but the complexity of accessing caches increases
Solution Approach 1:
The patent creates a universal cache access interface through the memory controller that serves all processors. The routing crossbar provides a multi-functional path that can route requests from any processor to any L2 cache, allowing parallelism to scale without proportionally increasing access complexity.
Solution Approach 2:
The patent moves L2 caches from the processor dimension to the memory dimension, organizing them on the memory side of the routing crossbar. This dimensional reorganization allows processors to access caches through the routing fabric without direct point-to-point coupling, enabling parallelism to increase while access complexity remains managed through the memory controller.
3Loss of time
If processors read from CPU system memory, then data can be transferred, but the number of clock cycles increases compared to direct cache writing
Solution Approach 1:
The patent implements preliminary action by allowing the CPU to write data directly to L2 caches in advance of processor needs. This pre-positioning of data in the cache hierarchy eliminates the need for processors to read from slower system memory, reducing clock cycle count and improving data transfer speed.
Solution Approach 2:
The patent uses copying by creating cache copies of data in L2 caches before processors need to access them. Instead of processors reading directly from CPU system memory, the data is copied to the cache hierarchy in advance, providing faster access and reducing the time penalty of memory operations.
Data Source
AI summary
In a multiprocessor system level 2 caches are positioned on the memory side of a routing crossbar rather than on the processor side of the routing crossbar. This configuration permits the processors to store messages directly into each other's caches rather than into system memory or their own coherent caches. Therefore, inter-processor communication latency is reduced.