Adaptive L2 Cache Mesh for Multi-Core SoC Memory Sharing
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Solution Overview
Problem
In multi-processor system-on-chip (SoC) devices, L2 caches cannot be shared between processors, leading to waste of memory and increased latency due to the need for snoop operations when searching non-local caches, which results in delays and inefficiencies in memory access.
Innovation Solution
A system and method where each core in a multi-core SoC can independently access a dedicated external memory, with a mesh/bus connection between L1 and L2 caches allowing simultaneous search of all L2 caches in case of an L1 miss, eliminating the need for snoop operations and enabling dynamic sharing of L2 caches between enabled processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If L2 caches are dedicated to each processor core, then cache access speed is improved, but memory utilization efficiency deteriorates when processors are shutdown
Solution Approach 1:
The patent implements dynamic L2 cache sharing where cache allocation changes based on processor operational states. When processors are shutdown, their L2 caches become available for sharing with active processors through a mesh network, allowing the system to adapt cache utilization to current workload requirements and avoid wasting memory resources.
2Measurement precision
If snoop operations are used to search non-local L2 caches, then cache hit accuracy is improved, but access latency increases significantly
Solution Approach 1:
The patent segments the L2 cache search operation into parallel independent searches across multiple cache nodes in the mesh network. Instead of sequential snoop operations that propagate through the entire system, each L2 cache node independently searches its local cache simultaneously, dramatically reducing access latency while maintaining complete cache hit accuracy through the coordinated mesh architecture.
3Adaptability or versatility
If L2 caches are shared between processors, then memory utilization is improved, but system complexity increases due to coordination requirements
Solution Approach 1:
The patent implements a universal mesh network interconnect that serves multiple functions: it enables L2 cache sharing between processors, provides a pathway for memory access, and facilitates system-wide communication. This multi-functional approach allows L2 cache sharing without requiring separate dedicated coordination mechanisms, thereby reducing overall system complexity while improving memory utilization.
Data Source
AI summary
A system and method are provided for adaptively configuring L2 cache memory usage in a system of microprocessors. A system-on-chip (SoC) is provided with a plurality of n selectively enabled processor cores and a plurality of n L2 cache memories. The method associates each L2 cache with a corresponding processor core, and shares the n L2 caches between enabled processor cores. More explicitly, associating each L2 cache with the corresponding processor core means connecting each processor core to its L2 cache using an L2 data/address bus. Sharing the n L2 caches with enabled processors means connecting each processor core to each L2 cache via a data/address bus mesh with dedicated point-to-point connections.