L2 Cache Controller Multi-Buffer Pipelining for Hazard Stall Reduction
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Solution Overview
Problem
In data processing systems with second-level memory, existing technologies face challenges in managing multiple access requests from different requestors to various endpoints efficiently, leading to interference and performance degradation, especially when resources are conflicted or external influences occur.
Innovation Solution
A data processing system with a level two memory controller that includes four arbitration units to select and prioritize requests, ensuring independent operations across different pipelines, maintaining read/write ordering, and utilizing multiple buffers to maintain high throughput even in the presence of external stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple access requests from different requestors are managed in a shared memory controller, then resource utilization improves, but interference and performance degradation occur
Solution Approach 1:
The memory controller is segmented into multiple independent pipelines (first pipeline for CPU requests, second pipeline for DMA requests, third pipeline for internal cache requests). Each pipeline has dedicated arbitration units and buffer units, allowing simultaneous independent operation without mutual interference, thus maintaining high resource utilization while ensuring stable performance for each requestor type
Solution Approach 2:
Pipeline arbitration units act as intermediaries between different requestors and the shared memory resources. These arbitration units independently manage and prioritize requests from different sources, coordinating access to prevent conflicts while maximizing overall resource utilization through fair scheduling
2Productivity
If a single pipeline is used for memory access, then device complexity is reduced, but throughput and parallelism are limited
Solution Approach 1:
The controller architecture is divided into three parallel pipelines, each handling specific types of requests independently. This segmentation enables simultaneous processing of multiple request types, achieving high throughput while keeping each individual pipeline relatively simple and manageable
Solution Approach 2:
The system transitions from a single-dimensional sequential processing model to a multi-dimensional parallel processing model by introducing multiple pipelines operating simultaneously. Each pipeline operates in its own dimension of execution, allowing throughput to scale with the number of pipelines while maintaining individual pipeline simplicity
3Reliability
If external memory responses are awaited synchronously, then data accuracy is ensured, but latency increases due to external stalls
Solution Approach 1:
The buffer units pre-allocate storage space and prepare to receive external memory responses before the actual data transfer completes. This allows the memory controller to continue processing other requests without waiting for slow external memory operations, reducing latency while ensuring data accuracy through proper buffering and synchronization protocols
Solution Approach 2:
While one pipeline is waiting for external memory responses, other pipelines continue to process requests without interruption. The buffer units maintain continuous operation by decoupling the timing of request issuance from response receipt, ensuring that useful work continues throughout the system rather than stalling when external memory is slow
4Productivity
If multiple requestors share the same memory controller resources, then resource efficiency improves, but resource conflicts and stalls occur
Solution Approach 1:
Resources are segmented and dedicated to specific pipelines: CPU requests use the first pipeline with its dedicated arbitration and buffer units, DMA requests use the second pipeline with its own dedicated units, and internal cache requests use the third pipeline. This segmentation eliminates resource conflicts between different requestor types while maintaining high overall resource efficiency through parallel utilization
Solution Approach 2:
Each pipeline is self-sufficient with its own arbitration unit that independently manages its queue of requests and its own buffer units that handle its specific data flow. This self-service capability allows each requestor type to operate smoothly without being blocked or stalled by the activities of other requestors, while all pipelines collectively achieve high resource efficiency
Data Source
AI summary
This invention is a data processing system including a central processing unit, an external interface, a level one cache, level two memory including level two unified cache and directly addressable memory. A level two memory controller includes a directly addressable memory read pipeline, a central processing unit write pipeline, an external cacheable pipeline and an external non-cacheable pipeline.