L2 Cache PAP Residency Selection to Reduce Coherence Overhead
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Solution Overview
Problem
Cache memories in microprocessors can significantly impact performance due to access time and cache coherency issues, particularly in multi-processor systems, leading to inefficiencies and idle execution units.
Innovation Solution
Implementing a cache memory subsystem with a first-level cache and an N-way set associative second-level cache that uses physical address proxies (PAPs) to enhance cache coherency and reduce the amount of cache coherence-related information, allowing concurrent lookup and allocation of PAPs in a directory to improve access times and cache capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache memory stores comprehensive coherence information for each entry, then cache coherency is maintained, but cache capacity and access speed deteriorate due to increased entry size
Solution Approach 1:
The cache entry is segmented into multiple fields: tag field for address identification, data field for stored data, and a separate coherence state field. This segmentation allows the cache to maintain comprehensive coherence information while optimizing the allocation of entry space, balancing coherency requirements with cache capacity constraints.
Solution Approach 2:
The patent extracts and isolates specific coherence-related information into dedicated fields within the cache entry structure. By taking out only the essential coherence state indicators rather than storing complete coherence metadata, the system maintains coherency while reducing the space consumed by coherence information, thereby preserving cache capacity for actual data storage.
2Reliability
If cache memory stores comprehensive coherence information for each entry, then cache coherency is maintained, but access time increases due to larger entry size
Solution Approach 1:
The cache entry is segmented into multiple fields: tag field for address identification, data field for stored data, and a separate coherence state field. This segmentation allows the cache to maintain comprehensive coherence information while optimizing the allocation of entry space, balancing coherency requirements with cache capacity constraints.
Solution Approach 2:
The patent changes the parameter representation of coherence information by using compact state encodings rather than verbose metadata structures. By optimizing the bit-width and encoding scheme of coherence state fields, the system maintains accurate coherency tracking while minimizing the time required to read and write cache entries, thus reducing access time overhead.
3Reliability
If physical address proxies are allocated to all N ways in a set, then cache coherency is ensured, but device complexity and allocation overhead increase
Solution Approach 1:
Instead of allocating physical address proxies to all N ways in a set unconditionally, the patent implements partial allocation based on actual coherence requirements. The system allocates PAPs only to ways that contain valid data requiring coherence tracking, reducing allocation overhead and device complexity while maintaining coherency for the necessary subset of ways.
Solution Approach 2:
The cache coherence mechanism is designed to self-manage PAP allocation by automatically tracking which ways contain valid data and requiring coherence. The system uses validation bits and state machines within each cache entry to self-determine when PAP allocation is necessary, eliminating the need for complex external allocation logic and reducing overall device complexity.
Data Source
AI summary
A system and method for a cache memory subsystem including a first-level cache (L1) and an N-way set associative second-level cache (L2) inclusive of L1, including receiving a physical memory line address (PMLA) for allocation into L2, using a set index of the PMLA to select a set of N ways of L2, for each way of the selected set of N ways, forming a physical address proxy (PAP) for the PMLA, in which each formed PAP includes the set index portion and the corresponding way that uniquely identifies a corresponding one of the selected set of N ways of L2, for each of the N formed PAPs, receiving a corresponding indicator of whether the formed PAP is resident in L1, and selecting one of the selected N ways of L2 having a corresponding indicator indicating that the corresponding one of the N formed PAPs is not resident in L1.