L2 Cache Retention Mode for Leakage Power Reduction
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Solution Overview
Problem
Modern mobile electronic devices face increased power consumption and reduced battery life due to leakage current in data caches, especially during periods of low activity and rising temperatures, as conventional caches continue to draw voltage without corresponding benefits.
Innovation Solution
Implementing a system-on-chip (SoC) that puts caches into retention mode based on inactivity and temperature, using independently controlled banks within the L2 cache with idle counters to reduce voltage when inactive, and setting thresholds based on fabrication leakiness and temperature.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the cache continues to be supplied with voltage during periods of inactivity, then the cache remains ready for immediate access, but leakage current increases power consumption
Solution Approach 1:
The cache system dynamically adjusts its operational state based on activity conditions. The cache can transition between full-power mode (ready for immediate access) and retention mode (reduced voltage for lower power consumption). This dynamic state change allows the system to optimize between speed and power consumption based on actual usage patterns, resolving the contradiction between maintaining fast access and reducing leakage current during inactivity
Solution Approach 2:
The invention changes the voltage parameter supplied to the cache based on activity detection. When the cache is inactive for a threshold number of clock cycles, the voltage is reduced from full operational voltage to a lower retention voltage that maintains data integrity but significantly reduces leakage current. This parameter change directly addresses the contradiction by adjusting the electrical state to match operational needs
2Use of energy by moving object
If the cache is put into retention mode to reduce leakage current, then power consumption decreases, but the cache requires time to recover for subsequent accesses
Solution Approach 1:
The system performs preliminary actions by detecting cache inactivity and transitioning to retention mode before significant power loss occurs. The idle counter monitors access patterns and triggers the voltage reduction at an optimal point, allowing the cache to be prepared for potential future accesses while minimizing both power consumption and recovery time. This preliminary detection and response mechanism balances the trade-off between power savings and access readiness
3Use of energy by moving object
If the idle counter threshold is set low, then the cache enters retention mode frequently reducing power, but the cache may be accessed before recovery is complete
Solution Approach 1:
The system implements feedback through the idle counter mechanism that continuously monitors cache access patterns. The counter compares the current idle cycle count against a threshold value, and only triggers retention mode when the threshold is exceeded. This feedback mechanism ensures that the cache has been inactive long enough to safely enter retention mode without risking premature access attempts, thereby maintaining reliability while achieving power savings
Data Source
AI summary
Systems and methods for reducing leakage power in a L2 cache within a SoC. The L2 cache is partitioned into multiple banks, and each bank has its own separate power supply. An idle counter is maintained for each bank to count a number of cycles during which the bank has been inactive. The temperature and leaky factor of the SoC are used to select an operating point of the SoC. Based on the operating point, an idle counter threshold is set, with a high temperature and high leaky factor corresponding to a relatively low idle counter threshold, and with a low temperature and low leaky factor corresponding to a relatively high idle counter threshold. When a given idle counter exceeds the idle counter threshold, the voltage supplied to the corresponding bank is reduced to a voltage sufficient for retention of data but not for access.