L2 Cache as Unified Load Store Buffer
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Solution Overview
Problem
Existing cache systems require separate load and store buffers for data operations with external memory, consuming significant memory space and degrading performance in high-throughput applications like graphics processing.
Innovation Solution
A method where an intermediary cache processes read and write operations without separate load and store buffers by reserving cache lines within the data cache array, allowing for efficient scheduling and prioritization of data operations directly within the cache.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate load and store buffers are used for data operations with external memory, then data coherency can be maintained, but memory space is consumed significantly
Solution Approach 1:
The patent merges the L2 cache and load/store buffers into a unified cache structure. The L2 cache is configured to directly receive load requests from processing clusters and store received data in available cache lines, eliminating the need for separate load buffers. Similarly, store requests write directly to cache lines in the L2 cache, eliminating separate store buffers. This integration maintains data coherency while significantly reducing the memory space required for buffer operations.
2Productivity
If dedicated buffers are allocated for high throughput data operations, then data throughput can be maintained, but the amount of memory space required increases
Solution Approach 1:
The L2 cache is designed to serve multiple functions simultaneously: it acts as both a data cache for storing frequently accessed data and as a load/store buffer for handling data transfers between external memory and processing clusters. By making the L2 cache universal, the system maintains high data throughput for both cache operations and buffer operations without requiring additional dedicated buffer space, thus optimizing memory space utilization while preserving productivity.
3Ease of operation
If separate load and store buffers are implemented, then data transfer operations can be buffered, but device complexity increases
Solution Approach 1:
The patent extracts the buffering function from separate dedicated buffers and integrates it directly into the L2 cache structure. Load requests are buffered by storing received data directly in available cache lines within the L2 cache, and store requests are buffered by writing directly to cache lines in the L2 cache. This extraction of the buffering function from separate structures and its integration into the existing L2 cache simplifies the overall device complexity while maintaining the essential data transfer buffering capability.
Data Source
AI summary
One embodiment of the invention sets forth a mechanism for using the L2 cache as a buffer for data associated with read/write commands that are processed by the frame buffer logic. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves necessary cache lines for the read/write operations and transmits read commands to the frame buffer logic for processing. A data slice scheduler transmits a dirty data notification to the frame buffer logic when data associated with a write command is stored in an SRAM bank. The data slice scheduler schedules accesses to the SRAM banks and gives priority to accesses requested by the frame buffer logic to store or retrieve data associated with read/write commands. This feature allows cache lines reserved for read/write commands that are processed by the frame buffer logic to be made available at the earliest clock cycle.