L2 Cache Write-Allocate Merging for Non-Blocking Transactions
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Solution Overview
Problem
Existing multi-level cache systems face inefficiencies in cache allocation and transaction processing, particularly in handling cache coherence states and prioritization of transactions in the pipeline, leading to potential stalls and reduced performance.
Innovation Solution
Implementing random selection of cache ways in set associative caches and dynamic transaction arbitration in the pipeline stages to handle cache coherence states and prioritize transactions based on priority, allowing non-blocking transactions to bypass blocking ones, and enabling caching or non-caching modes based on configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache allocation follows strict coherence state checking, then cache coherence is maintained, but transaction processing speed decreases due to additional validation steps
Solution Approach 1:
The patent pre-determines cache line allocation by selecting a way in advance based on coherence states before the actual write transaction arrives. This preliminary way selection eliminates the need for complex runtime coherence checking during transaction processing, thereby maintaining cache coherence while improving transaction processing speed.
Solution Approach 2:
The patent dynamically adjusts the cache allocation strategy by checking coherence states and adapting way selection based on pending requests. The system transitions from static allocation to dynamic allocation that responds to real-time cache states, resolving the contradiction between maintaining coherence and processing speed.
2Speed
If random way selection is used for cache allocation, then allocation speed increases, but cache performance degrades due to suboptimal cache line placement
Solution Approach 1:
The patent applies different selection strategies to different ways within the same cache set. Instead of uniform random selection, it evaluates coherence states locally for each way and selects based on specific criteria (invalid states, non-pending requests). This localized quality assessment improves cache performance while maintaining fast allocation.
Solution Approach 2:
The patent changes the selection parameter from purely random to coherence-state-aware selection. By incorporating coherence state information into the way selection process, it transforms the allocation strategy to balance speed and performance, selecting ways that are both available and likely to improve cache hit rates.
3Reliability
If cache ways are reserved for pending requests, then coherence is maintained, but cache allocation flexibility decreases leading to stalls
Solution Approach 1:
The patent applies partial reservation by checking coherence states and selecting ways that are either invalid or have non-pending requests. It doesn't require full reservation of all ways with pending requests, but rather selects from the subset of ways that are safe to allocate. This partial action maintains coherence while preserving allocation flexibility.
Data Source
AI summary
A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.