L2 Memory Banking for Concurrent CPU and DMA Access
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Solution Overview
Problem
Digital data processors face challenges in efficiently handling CPU and DMA traffic in second-level memory, requiring simultaneous access with high throughput and reduced latency, while existing solutions complicate memory design and increase power consumption.
Innovation Solution
A banking technique for level two memory that facilitates efficient data transfers by allocating CPU and DMA streams across multiple physical and virtual banks, optimizing access widths to achieve pipelined operations without introducing stalls.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU and DMA streams access level two memory simultaneously, then data transfer efficiency is improved, but memory access conflicts and stalls increase
Solution Approach 1:
The level two memory is divided into multiple banks (e.g., four banks) that can be independently accessed. CPU and DMA streams are allocated to different banks, allowing simultaneous access without conflicts. This segmentation enables parallel memory operations and eliminates stalls caused by single-bank access constraints.
Solution Approach 2:
The patent introduces a bank dimension to the memory access architecture. Instead of single-dimensional sequential access, memory is organized with multiple banks that can be accessed in parallel across different dimensions. This allows CPU and DMA operations to proceed simultaneously by accessing different banks, effectively adding a temporal parallelism dimension to the memory system.
2Productivity
If memory bandwidth is increased to handle multiple sources, then throughput is improved, but device complexity and power consumption increase
Solution Approach 1:
Rather than increasing the bandwidth of a single memory interface, the patent segments the memory into multiple banks with individual access ports. This allows multiple data sources (CPU, DMA) to access memory simultaneously through different banks, achieving high throughput without requiring a single high-complexity wide interface. Each bank maintains simpler, standardized access logic.
Solution Approach 2:
The memory banking structure provides a universal interface that can handle multiple types of access requests (CPU reads, CPU writes, DMA transfers) through the same banked architecture. The same memory banks serve multiple functions and multiple masters, reducing the need for separate specialized memory interfaces for each data source and thereby reducing overall device complexity.
3Speed
If memory access latency is reduced for high performance, then system speed is improved, but access conflicts between multiple streams increase
Solution Approach 1:
By segmenting memory into multiple banks, the patent eliminates access conflicts between CPU and DMA streams. Each stream can access its allocated banks without waiting for other streams, ensuring consistent low latency performance. The segmentation physically separates access paths, making conflicts impossible rather than just reducing their probability.
Data Source
AI summary
The level two memory of this invention supports coherency data transfers with level one cache and DMA data transfers. The width of DMA transfers is 16 bytes. The width of level one instruction cache transfers is 32 bytes. The width of level one data transfers is 64 bytes. The width of level two allocates is 128 bytes. DMA transfers are interspersed with CPU traffic and have similar requirements of efficient throughput and reduced latency. An additional challenge is that these two data streams (CPU and DMA) require access to the level two memory at the same time. This invention is a banking technique for the level two memory to facilitate efficient data transfers.