Dynamic L2P Buffer Expansion for Random Write Workloads

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Solution Overview

Problem

The overhead associated with loading and off-loading of the logical-to-physical (L2P) address translation table data in non-volatile memory devices, such as NAND, affects the performance of host read and write operations, particularly during random write workloads, due to conflicts between buffer flushing and host write operations.

Innovation Solution

Expanding the buffer size used to store portions of the L2P address translation table during random write operations to reduce the frequency of flushing and updating, thereby improving overall memory system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the buffer size is increased to store more L2P address translation table data, then the frequency of buffer flushing is reduced and performance is improved, but the device complexity and memory capacity requirements increase

Engineering Contradiction:
Improvememory system performanceVSAvoidbuffer management complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The buffer size is made dynamically adjustable based on workload characteristics. The system transitions from a fixed buffer configuration to a dynamic one where the buffer size can be expanded or contracted according to the intensity and type of operations (e.g., sequential vs. random writes), resolving the contradiction between performance and complexity by adapting rather than over-provisioning

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the parameter of buffer size from a static value to a variable that can be adjusted based on operational conditions. By monitoring workload patterns and adjusting buffer size accordingly, the system optimizes performance during high-intensity operations while maintaining acceptable complexity during normal operations

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If the buffer size is increased to reduce flushing frequency, then latency is reduced and response time is improved, but the volatile memory capacity required increases

Engineering Contradiction:
Improveoperation latencyVSAvoidvolatile memory capacity
Core Design Contradiction:
Loss of timeVSQuantity of substance

Solution Approach 1:

The buffer size is dynamically adjusted based on the intensity and duration of operations. During high-intensity random write workloads, the buffer is expanded to minimize flushing and reduce latency. During normal workloads, the buffer remains smaller to conserve volatile memory capacity, thus resolving the contradiction between reducing latency and minimizing memory usage

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs preliminary analysis of workload patterns to determine when buffer expansion is necessary. By anticipating high-intensity operations and proactively expanding the buffer before performance degradation occurs, the system reduces latency without requiring continuous large buffer allocation, thereby optimizing the balance between response time and memory capacity

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12541465B2Buffer expansion for random write operations
Publication Date: 2026.02.03 MICRON TECHNOLOGY INC
  • US12541465B2 patent drawing
  • US12541465B2 patent drawing
  • US12541465B2 patent drawing

AI summary

Methods, systems, and devices for buffer expansion for random write operations are described. Implementations provide buffer expansion for random write operations used to store L2P address translation table data under certain recognized operation workloads. Memory locations within the memory system controller are typically allocated for use during various operations. During different operational workloads, the amount of memory required for each of these different allocated memory areas may vary. By recognizing the entry of the memory system into a workload of random write operations, the memory system controller may expand a buffer size used to store the portion of the L2P address translation table data used during the write operations to retain larger portions of the L2P address translation table in the buffer.