L2P Mapping Cache Architecture for Lower-DRAM Memory Subsystems
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Solution Overview
Problem
The increasing density of NAND memory devices leads to a larger logical-to-physical (L2P) table size, necessitating increased DRAM requirements, which is infeasible due to stable DRAM densities and complicates the hardware layout, while conventional approaches like increasing mapping indirection size or using paging result in performance and endurance losses.
Innovation Solution
Storing the L2P table in a NAND memory device, utilizing a read cache in DRAM for quick look-ups, and employing a secondary FTL with a reduced indirection unit size to manage cache misses, reducing DRAM footprint and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If L2P table size increases to support rising NAND cell densities, then memory capacity and addressing capability improve, but DRAM requirements and system complexity increase
Solution Approach 1:
The L2P table is divided into multiple segments or partitions that can be managed separately. This segmentation allows the system to handle large L2P tables by processing smaller chunks at a time, reducing the peak DRAM requirements while maintaining the ability to support large NAND cell densities.
Solution Approach 2:
The patent introduces a hierarchical caching structure that adds another dimension to L2P table management. By implementing multiple levels of caching (e.g., L1 cache, L2 cache) with different sizes and access characteristics, the system can support large L2P tables without linearly increasing DRAM requirements, as not all entries need to be simultaneously available in high-speed memory.
2Quantity of substance
If flash memory is used for caching L2P table, then DRAM requirements are reduced, but performance and endurance deteriorate
Solution Approach 1:
The patent applies local quality by implementing a hybrid caching architecture where frequently accessed L2P table entries are cached in fast DRAM, while less frequently accessed entries are stored in slower flash memory. This allows the system to reduce overall DRAM usage while maintaining high performance for critical operations, as each region of the cache serves its specific access pattern requirements.
3Ease of manufacture
If conventional caching approaches are used, then implementation is simpler, but performance and endurance are compromised
Solution Approach 1:
The patent implements dynamic caching policies that adapt to workload characteristics and access patterns. The caching mechanism can dynamically adjust which L2P table entries are cached, for how long, and in which memory region, based on real-time performance metrics and access frequency. This dynamic approach maintains simple overall architecture while achieving superior performance through intelligent, adaptive cache management.
Data Source
AI summary
A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.