L2P Mapping Table Caching for SSD Random Read Performance

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Solution Overview

Problem

The increasing address space of memory devices in memory controllers leads to a larger occupancy of the logical to physical mapping table in RAM, affecting the performance of random read operations in SSDs and UFS devices.

Innovation Solution

A method is introduced to load the logical to physical mapping table into a cache of the memory controller by determining continuous address values, selecting a base physical address, and setting a base physical address offset, thereby compressing the mapping relationship and reducing cache space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the logical to physical mapping table is stored in RAM of the memory controller, then the mapping relationship can be maintained, but the memory occupancy increases due to continuous increase of address space

Engineering Contradiction:

Improvemapping relationship maintenanceVSAvoidmemory occupancy

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent extracts the mapping table from the main RAM memory and loads it into a dedicated cache memory within the memory controller. This separation allows the mapping table to be stored in a smaller, faster memory structure, reducing the overall memory occupancy while maintaining the mapping relationship functionality.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent divides the mapping table into segments and loads only the necessary segments into the cache memory. This segmentation approach allows selective loading of mapping entries based on current operational needs, reducing cache occupancy while maintaining required mapping relationships.

Inventive Principle:

Principle #1Segmentation

2Adaptability or versatility

If the logical to physical mapping table occupies larger memory space, then the address space can be accommodated, but the random read performance is affected

Engineering Contradiction:

Improveaddress space accommodationVSAvoidrandom read performance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent performs preliminary loading of the mapping table into the cache memory before random read operations are needed. This preliminary action ensures that the mapping table is readily available in fast cache memory, improving random read performance while accommodating the required address space.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces cache memory as an intermediary between the main RAM and the memory controller's processing units. This intermediary structure allows efficient access to mapping relationships without requiring the entire mapping table to reside in slow RAM, thus improving random read performance while maintaining address space accommodation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS12554638B2Loading logical to physical mapping table to cache of memory controller

Publication Date: 2026.02.17 YANGTZE MEMORY TECH CO LTD

AI summary

A method of operating a memory system is provided. A logical-to-physical (L2P) address mapping table is obtained in response to a data request instruction. Corresponding data is read from a memory device based on the L2P address mapping table. The L2P address mapping table includes a base physical address of continuous first physical addresses corresponding to first logic addresses and a base physical address offset corresponding to the continuous first physical addresses.