L2P Dual Address Encoding for Lower Multi-Page Read Latency
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Solution Overview
Problem
Large memory devices face challenges in managing logical-to-physical address mapping due to the size of L2P tables, which can exceed the capacity of on-chip DRAM, leading to increased read latency for multi-page data access, especially in systems lacking on-chip DRAM like Universal Flash Storage (UFS) devices.
Innovation Solution
Implement dual address encoding in L2P tables by packing multiple physical addresses into a single entry, allowing host devices to retrieve data from multiple physical addresses with a single read command, while maintaining compatibility with existing systems through duplicate entries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If L2P tables are made larger to accommodate more physical addresses, then mapping capacity is improved, but read latency increases due to exceeding on-chip DRAM capacity
Solution Approach 1:
The patent transitions from a one-dimensional linear address mapping to a two-dimensional dual-address encoding scheme. Each L2P table entry now contains two physical addresses instead of one, effectively doubling the mapping capacity without increasing the number of table entries. This dimensional change in address encoding allows the system to access more pages through the same on-chip DRAM capacity, resolving the contradiction between mapping capacity and read latency.
Solution Approach 2:
The patent merges multiple physical addresses into a single L2P table entry by implementing dual-address encoding. Instead of requiring separate entries for each physical address, the system combines two addresses per entry, thereby reducing the total number of entries needed and fitting within on-chip DRAM capacity while maintaining expanded mapping capability. This merging directly addresses the contradiction by increasing effective capacity without proportionally increasing memory footprint.
2Productivity
If multiple physical addresses are stored in single L2P entry, then read operation efficiency is improved, but address encoding complexity increases
Solution Approach 1:
The patent segments the address encoding into distinct components: a first physical address and a second physical address are stored as separate fields within the L2P table entry. This segmentation allows the system to maintain structured, predictable memory layout while achieving dual-address functionality. The segmentation simplifies the encoding complexity by breaking down the multi-address requirement into manageable, standardized fields that can be processed systematically during read operations.
Solution Approach 2:
The patent implements preliminary action by pre-encoding multiple physical addresses into the L2P table structure during system initialization or data setup. The dual-address encoding is established in advance, allowing the host device to retrieve multiple pages through a single read command without requiring complex real-time address resolution. This preliminary encoding arrangement reduces operational complexity while improving read efficiency.
3Loss of time
If dual address encoding is implemented, then read latency is reduced, but compatibility with existing systems may be compromised
Solution Approach 1:
The patent applies universality by designing the L2P table entry structure to serve multiple functions: it can store either a single physical address in the first field or combine multiple addresses across the first and second fields. This multi-functional design ensures that the dual-address encoding is backward compatible with existing single-address systems, while also enabling enhanced performance for systems that support the extended capability. The universal structure allows gradual adoption without forcing compatibility changes.
Data Source
AI summary
Methods, systems, and devices for dual address encoding for logical-to-physical mapping are described. A memory device may identify a first physical address corresponding to a first logical block address generated by a host device and a second physical address corresponding to a second (consecutive) logical block address generated by a host device. The memory device may store the first physical address and second physical address in a single entry of a logical-to-physical mapping table that corresponds to the first logical block address. The memory device may transmit the logical-to-physical table to the host device for storage at the host device. The host device may subsequently transmit a single read command to the memory device that includes the first physical address and the second physical address based on the logical-to-physical table.