Hierarchical Logical-to-Physical Mapping for Large NAND with Reduced DRAM
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Solution Overview
Problem
Conventional memory sub-systems face challenges in managing increased NAND sizes due to the high demand for DRAM, leading to performance impacts and write amplification, especially with random read and write operations, which affect endurance and efficiency.
Innovation Solution
Implementing a reduced-size logical-to-physical mapping table by storing block numbers and page table indices, reducing DRAM requirements while maintaining performance through optimized page table searches and garbage collection processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a full logical-to-physical mapping table is maintained to support increased NAND sizes, then address mapping capability is improved, but DRAM size requirements increase
Solution Approach 1:
The mapping table is segmented into a hierarchical structure with a reduced L2P table storing only block numbers and page table indices, and multiple P2L mapping tables storing the actual logical-to-physical mappings. This segmentation allows the system to maintain large NAND capacity mapping capability while using minimal DRAM for the L2P table.
Solution Approach 2:
The patent introduces a new dimensional organization by creating multiple P2L mapping tables (P2L0, P2L1, etc.) that are indexed by the L2P table. This multi-dimensional structure replaces the traditional single flat L2P table, enabling the system to map large address spaces with reduced DRAM requirements.
2Ease of manufacture
If DRAM size is reduced to lower costs, then device cost is improved, but mapping table search time increases
Solution Approach 1:
The L2P table is pre-populated with block numbers and page table indices during memory initialization and wear-leveling operations. This preliminary action ensures that when a mapping search is needed, the system can immediately use the pre-computed indices to directly access the appropriate P2L table without performing extensive searches.
Solution Approach 2:
The L2P table acts as an intermediary that bridges the gap between logical addresses and physical locations. By storing block numbers and page table indices as intermediate data, the system enables rapid two-stage lookup: first in the compact L2P table, then in the appropriate P2L table, thereby reducing overall search time despite reduced DRAM size.
3Quantity of substance
If a reduced L2P table is used to decrease DRAM requirements, then DRAM size is reduced, but write amplification may increase
Solution Approach 1:
The system implements feedback mechanisms where the controller monitors write operations and uses the L2P table structure to optimize wear-leveling decisions. By tracking physical block usage through the hierarchical mapping, the controller can make informed decisions about data placement that minimize write amplification while maintaining the reduced L2P table structure.
Solution Approach 2:
The patent changes the structural parameters of the mapping table from a traditional flat structure to a hierarchical structure with indices. This parameter change enables the system to maintain efficient write operations by allowing rapid identification of target physical blocks through the indexed structure, thereby reducing the number of write operations needed while using less DRAM.
Data Source
AI summary
A logical-to-physical (L2P) data structure comprising a plurality of L2P table entries is maintained on the volatile memory device. Each L2P table entry comprises a block number and a page table index corresponding to the non-volatile memory device. A plurality of physical-to-logical (P2L) data structures each comprising a plurality of P2L table entries is maintained on the volatile memory device. Each of the plurality of P2L data structures corresponds to a portion of the L2P data structure.