L2P Mapping Flags for Bypassing Sequential Data Table Lookups
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Solution Overview
Problem
Existing memory devices face increased read latency and unnecessary operations due to the need to navigate multi-level logical-to-physical (L2P) tables, especially when data is sequentially stored, as they require accessing terminal L2P tables, which consume resources and cause wear on NAND memory cells.
Innovation Solution
Implementing a flag in second-level L2P table entries to indicate whether the entry points directly to sequential data, allowing the memory device to bypass the terminal L2P table, thereby optimizing read operations and reducing unnecessary table lookups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple level L2P table lookups are performed to access sequentially stored data, then mapping accuracy is maintained, but read latency increases and resources are consumed
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing offset values in the L2P table entries during data writing. When sequential data is written, the system pre-computes the offset from the starting physical address to each subsequent data location and stores this information in advance. During reading, this pre-stored offset allows direct calculation of physical addresses without requiring multiple L2P table lookups, thus reducing read latency while maintaining mapping accuracy.
2Measurement precision
If multiple level L2P table lookups are performed, then data location accuracy is improved, but resource consumption increases
Solution Approach 1:
The system performs preliminary action by pre-calculating offset values and storing them in the L2P table during the write operation. This pre-computation stores the relative position information from the starting address to each data location. During subsequent read operations, the memory device can directly compute physical addresses using these pre-stored offsets, avoiding the need for multiple energy-consuming L2P table lookups while maintaining accurate data location information.
3Measurement precision
If terminal L2P table updates are performed frequently, then mapping accuracy is maintained, but NAND Flash memory space is consumed and memory cell wear increases
Solution Approach 1:
The patent applies segmentation by dividing the L2P table into multiple levels (first-level, second-level, and terminal third-level tables). The first-level table stores mappings for larger address ranges with coarser granularity, the second-level table provides intermediate mappings, and the terminal table handles specific detailed mappings. This hierarchical segmentation allows the system to maintain mapping accuracy for frequently accessed data while reducing the size and update frequency requirements for the terminal L2P table, thereby conserving NAND Flash memory space and reducing memory cell wear.
Solution Approach 2:
The system performs preliminary action by pre-calculating and storing offset values in the L2P table entries during write operations. This pre-computation of relative address offsets allows the terminal L2P table to store smaller, more compact entries that require less memory space. Additionally, since offsets are pre-calculated, the terminal table doesn't need to store complete physical addresses for all entries, reducing the overall table size and the frequency of updates needed to maintain mapping accuracy.
Data Source
AI summary
Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.