L2P Address Mapping Compression for Lower Host Transfer Overhead
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Solution Overview
Problem
Existing memory systems face inefficiencies in communicating and storing logical-to-physical (L2P) address mappings due to the large data transfer and storage requirements associated with fixed-size entries, which can increase processing latency and storage overhead.
Innovation Solution
The memory system reduces the amount of information transferred and stored by determining sequentially-mapped portions of the L2P mapping and transmitting indications of starting addresses and sizes, allowing for efficient address searching using search trees or hash tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If fixed-size entries are used for L2P mapping communication, then complete mapping information is transferred, but data transfer volume and storage requirements increase significantly
Solution Approach 1:
The patent segments the L2P mapping into two types of entries: full-size entries for sequentially-mapped portions and compact indications (starting address + size) for non-sequential portions. This segmentation allows the system to transfer only necessary mapping information rather than always transferring complete fixed-size entries, thereby reducing data transfer volume while maintaining information completeness where needed.
Solution Approach 2:
The patent extracts only the essential information (starting address and size) for non-sequential L2P mappings and transfers only this extracted information rather than the complete fixed-size entry. This extraction principle reduces the quantity of data transferred while preserving the necessary mapping relationships.
2Loss of information
If fixed-size L2P mapping entries are stored at the host system, then complete mapping data is available, but storage overhead increases
Solution Approach 1:
The patent segments storage requirements by maintaining full L2P mapping tables at the memory system level while storing only compact indications (starting address and size) at the host system level. This segmentation allows the host system to store minimal mapping information rather than complete fixed-size entries, reducing storage overhead while maintaining data availability through the memory system's full mapping tables.
Solution Approach 2:
The patent uses a copying approach where the memory system maintains the complete L2P mapping table as a reference, and the host system stores only a copy of the essential indications (starting address and size) for non-sequential portions. This copying strategy reduces host storage requirements while preserving mapping data availability through the reference copy at the memory system.
3Loss of information
If complete L2P mapping tables are transferred to host system, then full mapping information is obtained, but processing latency increases
Solution Approach 1:
The patent segments the L2P mapping transfer operation into two phases: first transferring only the compact indications for non-sequential portions (reducing transfer time), and secondly accessing the full mapping information from the memory system only when needed. This segmentation of the transfer process reduces processing latency while maintaining information completeness through the memory system's full mapping tables.
Solution Approach 2:
The patent applies partial action by transferring only the necessary compact indications rather than complete fixed-size entries for all mapping portions. This partial transfer approach reduces the time required to transfer mapping information to the host system while maintaining sufficient information completeness for most operations, with full details available on-demand from the memory system.
Data Source
AI summary
Methods, systems, and devices for transmitting logical-to-physical (L2P) address mapping to a host system are described. A memory system may be configured to determine portions of an L2P mapping that are sequential, and transfer indications of respective starting addresses and a respective size of such sequential mappings. For example, a memory system may be configured to transmit an indication of a starting logical address, a corresponding starting physical address (e.g., a physical address mapped to the starting logical address), and a size of a sequential mapping from the starting logical and physical addresses. In some such examples, search techniques may be adapted at the memory system, at the host system, or both to facilitate address searching with the revised L2P mapping structure (e.g., to leverage indications of starting addresses and lengths of sequential portions), such as implementing aspects of a search tree or hash table.