L2P Mapping Table Compression Using RLE for Low-Latency NAND Access
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Solution Overview
Problem
Current memory systems face challenges in expanding address ranges without degrading write performance or increasing read latency, due to limited cache storage for logical-to-physical (L2P) mapping tables in NAND storage devices.
Innovation Solution
Implementing a Run Length Encode (RLE) algorithm to decrease the average map entry size of L2P pointers, removing reserved and static bits, and packing the resulting bits into SRAM, while using a FIFO structure to manage map pages and handle cache limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the L2P mapping table size is increased to expand address range, then the address range capability is improved, but the cache storage requirement increases导致read latency increases
Solution Approach 1:
The patent extracts only the necessary variable bits from physical addresses, removing reserved and static bits that do not contribute to address range capability. This extraction reduces the average map entry size while maintaining the ability to address the required range, allowing more entries to fit in cache and reducing read latency.
Solution Approach 2:
The patent applies different encoding strategies to different portions of the physical address based on their variability. Frequently accessed or variable portions are encoded with more bits, while static or reserved portions are removed or encoded with fewer bits. This local optimization reduces overall entry size while maintaining address range capability where needed.
2Adaptability or versatility
If the L2P mapping table size is increased to expand address range, then the address range capability is improved, but the cache storage requirement increases导致write performance degrades
Solution Approach 1:
By extracting and removing reserved and static bits from the physical address encoding, the patent reduces the average map entry size. This reduction allows the cache to store more mapping entries within the same capacity, improving write performance by reducing cache misses and avoiding the performance degradation that would result from a larger cache requirement.
Solution Approach 2:
The patent changes the parameter of map entry size by dynamically encoding physical addresses based on their actual variability rather than using fixed maximum-size encodings. This parameter change reduces the average storage requirement per entry, allowing the system to maintain larger address range capability without proportionally increasing cache storage requirements, thereby preserving write performance.
3Quantity of substance
If reserved and static bits are removed from physical addresses, then the map entry size is reduced, but the address encoding complexity increases
Solution Approach 1:
The patent performs preliminary encoding of physical addresses using run-length encoding before storing them in the L2P mapping table. This preliminary action compresses sequences of identical or similar address bits, reducing the average map entry size. The encoding complexity is managed by performing the compression in advance during address translation setup, rather than during each access operation.
Solution Approach 2:
The patent creates a compressed representation (copy) of the physical address that eliminates reserved and static bits while preserving the essential address information. This copied encoded form is stored in the mapping table instead of the full original address, reducing entry size. The decoding process reconstructs the full address when needed, managing the complexity through standardized encoding/decoding routines.
Data Source
AI summary
Apparatus and methods are disclosed, including using a memory controller to generate an encoded physical address using a run length encoding (RLE) algorithm on a physical address to reduce a length of the encoded physical address, and storing the encoded physical address as a map entry of a logical-to-physical (L2P)) table in a cache random access memory of the memory controller.