L2P Mapping Granularity by Storage Sub-Region for Random I/O
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory devices face inefficiencies in mapping table granularity, leading to suboptimal performance in random read and write operations, particularly in NAND storage devices, due to the large size of the logical-to-physical mapping table that cannot fit entirely in the cache, impacting user experience and resource utilization.
Innovation Solution
Partition the storage device into regions with customized L2P mapping table granularities tailored to specific use cases, optimizing performance by assigning different granularities to different regions based on usage, and utilizing SRAM efficiently to store mapping tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single granularity is used for the entire L2P mapping table, then the device complexity is reduced, but the random read and write performance deteriorates due to inability to optimize for different usage patterns
Solution Approach 1:
The memory array is divided into multiple portions (e.g., first portion for operating system, second portion for key applications, third portion for other applications), each with its own customized L2P mapping table granularity. This segmentation allows each region to be optimized for its specific usage pattern, improving overall random read and write performance while managing complexity through structured organization.
Solution Approach 2:
Different granularities are assigned to different portions of the memory array based on their specific usage requirements. The first portion uses a first granularity optimized for OS operations, the second portion uses a second granularity for key applications, and the third portion uses a third granularity for other applications. This local optimization ensures each region performs optimally for its designated purpose.
2Quantity of substance
If the L2P mapping table is made large to cover the entire memory array, then the mapping coverage is improved, but the SRAM cache utilization deteriorates because the entire table cannot fit in cache
Solution Approach 1:
The large L2P mapping table is segmented into multiple smaller tables corresponding to different memory portions. Each smaller table can be individually loaded into the SRAM cache when needed, improving cache utilization efficiency. The mapping table for the first portion, second portion, and third portion are managed separately, allowing selective caching based on access patterns.
Solution Approach 2:
Instead of loading the entire large L2P mapping table into SRAM cache (which cannot accommodate it), only the relevant portion of the mapping table corresponding to currently accessed memory regions is loaded into cache. This partial loading approach ensures efficient SRAM utilization while maintaining the ability to map the entire memory array.
3Adaptability or versatility
If different granularities are assigned to different portions of the memory array, then the adaptability to different usage patterns is improved, but the device complexity increases due to multiple mapping table configurations
Solution Approach 1:
The memory array is divided into distinct portions (first portion for operating system, second portion for key applications, third portion for other applications), each with customized L2P mapping table granularity. This segmentation provides adaptability to different usage patterns while managing complexity through clear structural organization and dedicated management for each portion.
Data Source
AI summary
Apparatus and methods are disclosed, including using a memory controller to partition a memory array into a first portion and a second portion, the first portion and second portion having non-overlapping logical block addressing (LBA) ranges. The memory controller assigns a first granularity of a first logical-to-physical (L2P) mapping table entry for the first portion of the memory array designated for a first usage, and a second granularity of a second L2P mapping table entry for the second portion of the memory array designated for a second usage, where the second granularity is not equal to the first granularity. The memory controller stores the first granularity and the second granularity in the memory array, and stores at least a portion of the first L2P mapping table entry and the second L2P mapping table entry in an L2P cache of the memory controller.


