L2P Table Compression Using Data-Aligned Physical Address Mapping
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Solution Overview
Problem
As memory systems grow in size and complexity, the logical-to-physical (L2P) tables used for mapping logical block addresses to physical addresses become larger and less efficient, leading to increased latency and decreased read, write, and erase speeds due to higher memory usage and complexity.
Innovation Solution
The implementation of data alignment techniques for L2P table compression, where logical block addresses are used as indices for modulo operations to generate partial physical addresses, reducing the size and complexity of the L2P table and improving memory efficiency by partitioning shared memory into sections for efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the L2P table size increases to accommodate more mappings, then the mapping capacity is improved, but the memory usage and latency increase
Solution Approach 1:
The physical address is divided into two portions: a first portion derived from the L2P table lookup and a second portion generated through modulo operation on the LBA. This segmentation allows the L2P table to store only essential mapping information while the full physical address is reconstructed through computation, reducing table size requirements.
Solution Approach 2:
The patent transitions from storing complete physical addresses in the L2P table to storing only partial address information and deriving the complete address through mathematical operations. This dimensional reduction in the table entry size enables larger mapping capacity with reduced memory usage.
2Adaptability or versatility
If the L2P table size increases to accommodate more mappings, then the mapping capacity is improved, but the latency and read/write speeds decrease
Solution Approach 1:
By segmenting the address into portions that can be derived through fast computational operations rather than storing complete addresses, the patent reduces the amount of data that needs to be fetched and processed, thereby reducing latency while maintaining large mapping capacity.
Solution Approach 2:
The patent replaces the mechanical approach of storing complete physical addresses in memory with a computational approach using modulo operations and bit manipulation. This substitution enables faster address derivation through arithmetic operations rather than memory access, reducing latency.
3Quantity of substance
If the L2P table entry size is reduced through compression, then the memory efficiency is improved, but the address translation complexity increases
Solution Approach 1:
The patent uses mathematical operations (modulo arithmetic and bit shifting) to replace complex data structures for address compression. This substitution achieves memory efficiency through computation rather than through complex data structures, keeping the implementation relatively simple.
Solution Approach 2:
The patent changes the representation of physical addresses from complete address storage to partial address storage with computational derivation. By changing the parameter of how addresses are represented and generated, the patent achieves compression while maintaining translation functionality through well-defined mathematical operations.
Data Source
AI summary
Methods, systems, and devices for data alignment for logical to physical table compression are described. A controller coupled with the memory array may receive a command to access a logical block address associated with a memory device. In some cases, a first portion of a physical address of the memory device associated with the logical block address may be identified. The controller may perform an operation on the logical block address included in the command and identify a second portion of the physical address based on performing the operation. The physical address of the memory device may be accessed based on identifying the first portion and the second portion.