L2P Table Compression Using Exception Lists and Logical Trees

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Solution Overview

Problem

The increasing storage capacity of non-volatile memory systems necessitates a larger volatile memory for efficient L2P address translation, leading to increased physical size, power consumption, and manufacturing costs, while existing L2P table swapping techniques cause latency and wear out the memory system.

Innovation Solution

Implementing L2P table compression using an exception list and a logical tree to reduce the size of volatile memory required, by compressing information associated with address ranges and maintaining a larger address range in volatile memory, thereby increasing the likelihood of cache hits and reducing latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the storage capacity of non-volatile memory systems is increased, then the L2P table size must be increased to maintain efficient address translation, but this leads to increased physical size, power consumption, and manufacturing costs of volatile memory

Engineering Contradiction:

Improveaddress translation efficiencyVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSUse of energy by stationary object

Solution Approach 1:

The patent extracts only the essential L2P mapping information needed for address translation and stores it in a compressed format in volatile memory. By taking out only the critical address range information and compression metadata rather than storing complete L2P tables, the system maintains address translation efficiency while significantly reducing volatile memory requirements and associated power consumption.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter representation of L2P data by encoding address ranges in a compressed format rather than storing complete address mappings. This parameter transformation reduces the volume of data stored in volatile memory, thereby reducing physical size, manufacturing costs, and power consumption while preserving the ability to perform efficient address translation.

Inventive Principle:

Principle #35Parameter changes

2Area of stationary object

If the L2P table size is increased to support larger storage capacity, then the physical size and manufacturing costs of memory systems increase, but reducing L2P table size causes more frequent accesses to non-volatile memory increasing latency

Engineering Contradiction:

Improvephysical footprintVSAvoidaccess latency

Core Design Contradiction:

Area of stationary objectVSLoss of time

Solution Approach 1:

The patent applies asymmetry by storing L2P mapping information differently based on access patterns and address range characteristics. By identifying and compressing frequently accessed address ranges with specific patterns, the system maintains low latency for critical operations while reducing overall volatile memory requirements, thus decreasing physical footprint without significantly increasing access latency.

Inventive Principle:

Principle #4Asymmetry

3Speed

If more volatile memory is allocated for L2P address translation, then address translation speed is improved, but manufacturing costs and physical size of the memory system increase

Engineering Contradiction:

Improveaddress translation speedVSAvoidmanufacturing costs

Core Design Contradiction:

SpeedVSEase of manufacture

Solution Approach 1:

The patent creates a compressed copy of essential L2P mapping information that can be stored in smaller volatile memory. By generating a compact representation of address ranges and their corresponding physical locations, the system maintains fast address translation speed while reducing the amount of volatile memory needed, thereby lowering manufacturing costs.

Inventive Principle:

Principle #26Copying

4Ease of manufacture

If L2P table swapping techniques are used to reduce volatile memory usage, then manufacturing costs decrease, but latency increases and memory system wear increases

Engineering Contradiction:

Improvemanufacturing costsVSAvoidmemory system wear

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent performs preliminary compression of L2P mapping information before storing it in volatile memory. By pre-processing the address translation data into a compressed format, the system eliminates the need for frequent swapping operations during runtime, thereby reducing memory wear and maintaining reliability while still achieving cost reductions through reduced volatile memory usage.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12524339B2Logical-to-physical table compression using an exception list and a logical tree

Publication Date: 2026.01.13 MICRON TECHNOLOGY INC

AI summary

In some implementations, a memory apparatus may receive a command indicating a logical block address (LBA) that is associated with a logical-to-physical (L2P) table. The memory apparatus may perform a lookup operation associated with a compressed version of an address range of the L2P table to identify a physical address in non-volatile memory associated with the LBA, wherein the compressed version is stored in a volatile memory of the memory apparatus, wherein the compressed version is associated with an exception list that indicates physical addresses for respective LBAs, included in the address range, that are associated with non-sequential physical addresses, and wherein the compressed version is associated with a binary tree that indicates locations in the exception list associated with the respective LBAs. The memory apparatus may perform, based on the command, an action associated with the physical address.