L2P Table Paging for Fast Load and Power-Loss Recovery

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Solution Overview

Problem

Current L2P table management techniques in memory devices result in high latency, slow response times, and data loss during unexpected power down events due to inefficient transfer of mappings between volatile and non-volatile memory, leading to large memory overhead and extended time-to-ready times.

Innovation Solution

Implementing a system that transfers a limited quantity of current L2P mappings from volatile to non-volatile memory during runtime, using changelogs and journals to manage updates, reducing memory overhead and die footprint, and enabling fast L2P table load times upon power up.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If L2P mappings are transferred from volatile to non-volatile memory during runtime, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata retention during power downVSAvoidmemory management system
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The L2P table is segmented into multiple pages, with only the currently active page residing in volatile memory. This segmentation allows the system to maintain reliability by having backup copies in non-volatile memory while keeping the volatile memory footprint small and manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary actions by maintaining backup L2P table pages in non-volatile memory before power down events occur. This ensures that if power is lost unexpectedly, the mappings are already preserved and can be quickly restored without data loss.

Inventive Principle:
Principle #10Preliminary action

2Speed

If L2P tables are stored in volatile memory, then speed is improved, but reliability deteriorates during unexpected power down

Engineering Contradiction:
ImproveL2P mapping access timeVSAvoiddata retention during power loss
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

Different portions of the L2P table have different storage locations based on their usage state. The currently active L2P page is stored in volatile memory for fast access, while backup pages are stored in non-volatile memory for reliability. This local quality differentiation optimizes both speed and reliability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The controller acts as an intermediary between volatile and non-volatile memory, managing the transfer and coordination of L2P table pages. It determines which pages to load into volatile memory and maintains appropriate backups in non-volatile memory, balancing speed and reliability requirements.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If all L2P mappings are transferred to non-volatile memory, then reliability is improved, but time consumption increases

Engineering Contradiction:
Improvemapping persistenceVSAvoidpower up time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Instead of transferring all L2P mappings to non-volatile memory, the system performs partial action by only transferring and maintaining backup copies of L2P pages. The actively used page remains in volatile memory for immediate access, while backups are prepared in non-volatile memory, achieving reliability without the time cost of complete transfer.

Inventive Principle:
Principle #16Partial or excessive action

4Speed

If L2P tables are loaded into volatile memory upon power up, then speed is improved, but memory overhead increases

Engineering Contradiction:
ImproveL2P table load timeVSAvoidmemory overhead
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The L2P table is divided into multiple pages that are loaded into volatile memory on-demand rather than all at once. Only the currently needed page is loaded, significantly reducing the memory overhead while maintaining fast access speed for active mappings.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12608310B2Logical to physical (L2P) address mapping with fast L2P table load times
Publication Date: 2026.04.21 MICRON TECHNOLOGY INC
  • US12608310B2 patent drawing
  • US12608310B2 patent drawing
  • US12608310B2 patent drawing

AI summary

A memory device may detect a memory operation that updates a level two volatile (L2V) entry stored in an L2V table. Each L2V entry in the L2V table may indicate a mapping between a respective logical block address (LBA) and a respective user data physical address in non-volatile memory. The memory operation may cause a mapping between an LBA indicated in the L2V entry and a user data physical address indicated in the L2V entry to become invalid. The memory device may store, in a volatile memory log, an indication of an LBA region that includes the LBA. The memory device may detect that an L2 transfer condition, associated with the volatile memory log, is satisfied. The memory device may copy, from volatile memory to non-volatile memory, every L2V entry that indicates an LBA included in the LBA region based on detecting that the L2 transfer condition is satisfied.