L2P Indirection Table Segmentation in Persistent Memory SSDs
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Solution Overview
Problem
The existing storage devices face inefficiencies in managing the Logical to Physical (L2P) address indirection table, particularly due to its size dependency on user-capacity in solid state drives, which affects write performance and requires significant volatile memory for storage.
Innovation Solution
Storing the L2P address table in persistent memory within the solid state drive, allowing for increased performance and reduced dependency on volatile memory by using a combination of persistent and block addressable non-volatile memory, with a hardware assist circuitry for data transfer and metadata management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the L2P address table is stored in volatile memory, then read performance is improved, but the device requires significant volatile memory capacity which increases cost and complexity
Solution Approach 1:
The L2P address table is segmented into two parts: a hot portion frequently accessed during normal operations is stored in volatile memory for fast access, while a cold portion less frequently accessed is stored in persistent memory to reduce volatile memory requirements. This segmentation allows the system to maintain fast read performance for critical data while reducing overall volatile memory capacity needs.
Solution Approach 2:
Different portions of the L2P address table are assigned different storage locations based on their access patterns. The hot portion gets stored in volatile memory with fast access characteristics, while the cold portion is stored in persistent memory with slower but sufficient access characteristics. This local quality differentiation optimizes the balance between performance and memory capacity requirements.
2Adaptability or versatility
If the L2P address table size increases with user-capacity, then the table can accommodate more data, but write performance deteriorates due to increased update frequency and granularity
Solution Approach 1:
The L2P address table is segmented into hot and cold portions based on access patterns. The hot portion with frequent updates is stored in volatile memory to maintain fast write performance, while the cold portion with less frequent updates is stored in persistent memory. This segmentation allows the system to accommodate large user-capacity while maintaining write performance by isolating high-frequency write operations from the persistent memory storage.
Solution Approach 2:
Volatile memory acts as an intermediary between the persistent memory and the active data structures. It buffers the hot portion of the L2P address table, absorbing frequent write operations and reducing the granularity of updates that reach persistent memory. This intermediary layer protects write performance by filtering out high-frequency, low-impact updates before they affect the persistent storage.
3Speed
If more volatile memory is used to store the L2P address table, then access speed is improved, but device complexity and cost increase
Solution Approach 1:
The memory architecture is segmented into two functional zones: volatile memory for hot data with fast access requirements, and persistent memory for cold data with lower access requirements. This segmentation reduces the total volatile memory needed while maintaining fast access for critical operations, thereby reducing overall device complexity and cost.
Solution Approach 2:
Different quality levels of memory storage are applied locally to different portions of the L2P address table based on their access patterns. This allows the system to achieve fast access speeds for critical data without requiring fast memory for all data, simplifying the overall memory architecture and reducing costs.
Data Source
AI summary
A solid state drive with a Logical To Physical (L2P) indirection table stored in a persistent memory is provided. The L2P indirection table has a plurality of entries, each entry to store a physical block address in the block addressable memory assigned to a logical block address. The solid state drive including solid state drive controller circuitry communicatively coupled to the persistent memory and the block addressable memory. The solid state drive controller circuitry including a volatile memory to store a logical to physical address indirection table cache and circuitry to monitor the logical to physical address indirection table cache and to write dirty logical to physical entries in the logical to physical address indirection table cache to the logical to physical address indirection table in the persistent memory.


