L2P Mapping Table Switching for Faster NAND Flash Access
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Solution Overview
Problem
Existing memory access methods in computing devices, particularly those using NAND flash memory, suffer from inefficiencies due to cache misses and latency issues caused by outdated local logical-to-physical (L2P) mapping tables, which negatively impact user experience and performance.
Innovation Solution
A system-on-a-chip (SoC) with a control circuit that evaluates the active and inactive portions of local L2P mapping tables in dynamic random-access memory (DRAM) and dynamic random-access memory (DRAM) to determine the accuracy of local entries, allowing it to skip using outdated local tables and rely on more up-to-date external tables in SRAM for faster memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the local L2P mapping table is used for memory access, then memory access speed is improved, but cache misses occur when the local table is outdated
Solution Approach 1:
The system dynamically switches between using the local L2P mapping table and the external L2P mapping table based on the activity status of mapping entries. The control circuit determines whether to use the local table by evaluating the activity status of mapping entries, making the memory access path adaptive rather than static.
Solution Approach 2:
The system changes the operational parameter of the local L2P mapping table from always-used to conditionally-used based on the activity status parameter. When mapping entries are determined to be inactive, the system changes the access parameter to bypass the local table and use the external table instead.
2Reliability
If the local L2P mapping table is always accessed, then mapping accuracy is maintained, but access latency increases
Solution Approach 1:
The system extracts the activity status information from the local L2P mapping table and uses it to determine the access path. By taking out the activity status evaluation step, the system can selectively bypass the local table for inactive entries, removing unnecessary access steps and reducing latency.
Solution Approach 2:
When the control circuit determines that mapping entries are inactive, the system skips the local L2P mapping table access step entirely and proceeds directly to use the external L2P mapping table, rushing through the access process to reduce latency for known inactive entries.
3Speed
If the local L2P mapping table is used, then faster access is achieved, but outdated information causes incorrect mappings
Solution Approach 1:
The system uses feedback from the activity status of mapping entries to determine whether the local L2P mapping table should be used. The control circuit receives feedback about whether mapping entries are active or inactive and adjusts the access path accordingly, ensuring that outdated information does not lead to incorrect mappings.
Data Source
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AI summary
Systems and methods for fast memory access are disclosed. In one aspect, a processor such as, for example, a control circuit in a system on a chip (SoC) that couples to an external memory such as, for example a Universal File System (UFS) memory (e.g., a NAND flash memory) with a partial logical to physical (L2P) mapping table stored in the external memory as well as a local L2P mapping table stored in a local memory (e.g., dynamic random-access memory (DRAM)). The control circuit may evaluate what percentage of entries in the local L2P mapping table are active compared to inactive. If the number of inactive exceeds the number of active, the control circuit may send a read command without accessing the local L2P mapping table.