L2P Table Synchronization via Indicator Bits

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Solution Overview

Problem

Existing methods for synchronizing logical-to-physical (L2P) address mapping tables between host devices and storage devices are inefficient, leading to performance degradation due to large data transfers and overhead from memory management processes.

Innovation Solution

Implementing an indicator in the L2P table on the storage device to track synchronization status, allowing only changed entries to be transmitted for synchronization, and processing memory requests based on updated addresses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the entire L2P table is transmitted for synchronization, then the host device receives complete address mapping information, but the data transfer overhead increases significantly

Engineering Contradiction:
Improvesynchronization completenessVSAvoiddata transfer overhead
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent extracts only the changed portions of the L2P table (dirty entries) for transmission to the host device, rather than transmitting the entire table. This is achieved by tracking which entries have been modified since the last synchronization and selectively transmitting only those specific entries, thereby reducing data transfer overhead while maintaining synchronization completeness.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The L2P table is segmented into multiple entries, each with an associated indicator bit. The patent divides the synchronization task into individual entry-level updates rather than treating the table as a monolithic structure. This segmentation allows the system to transmit only the specific entries that have changed, rather than the entire table.

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If memory management processes update L2P tables frequently, then the address mapping remains current, but synchronization overhead increases

Engineering Contradiction:
Improveaddress mapping accuracyVSAvoidsynchronization efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies preliminary action by setting indicator bits on the storage device side before transmission occurs. When memory management processes update an L2P entry, the corresponding indicator bit is immediately set to mark it as dirty. This preliminary marking allows the host device to efficiently identify and retrieve only the changed entries during synchronization, rather than processing the entire table.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where the host device queries the storage device for changed entries based on the indicator bits. The storage device responds by providing only the entries that have been modified since the last synchronization. This feedback loop ensures that the host device receives accurate, up-to-date address mappings while minimizing synchronization overhead.

Inventive Principle:
Principle #23Feedback

3Loss of time

If the host device continuously monitors for L2P table changes, then synchronization timing is optimized, but the system complexity increases

Engineering Contradiction:
Improvesynchronization delayVSAvoidsynchronization mechanism complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary mechanism in the form of indicator bits that automatically track changes in the L2P table. These indicator bits serve as a mediator between the storage device's memory management processes and the host device's synchronization operations. Instead of requiring continuous monitoring or complex polling mechanisms, the indicator bits passively signal when updates are available, simplifying the synchronization mechanism while reducing synchronization delays.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12271303B2System and method for updating memory tables
Publication Date: 2025.04.08 QUALCOMM INC
  • US12271303B2 patent drawing
  • US12271303B2 patent drawing
  • US12271303B2 patent drawing

AI summary

Methods that may be performed by a host controller and a memory controller of a computing device. The method synchronizes memory tables between the storage device and a host device by modifying an indicator in a first memory table on the storage device in response to a change in a memory mapping, the first memory table mapping logical addresses to physical addresses of memory on the storage device, the indicator identifying one or more address mapping changes of the first memory table, notifying the host device that the first memory table has been modified, and transmitting to the host device at least a portion of the first memory table including the one or more address mapping changes. The storage device processes memory requests from the host device based on one or more addresses affected by the one or more address mapping changes.