L3 Cache Directory Management via Selective Coherency Updates
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Solution Overview
Problem
Conventional cache coherency protocols in multi-processor systems assume that coherency states from upper-level caches are copied into lower-level caches, leading to inefficiencies in managing cache coherency and increasing access latency.
Innovation Solution
The method involves comparing coherency data between upper and lower memory caches, determining the coherency state, and replacing the coherency value in the lower cache, with the introduction of an additional cache state (Ig) to indicate invalidity globally, allowing for more efficient communication and reduced latency by maintaining domain indicators even when no valid copy is cached.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coherency states are copied from upper-level caches to lower-level caches, then cache coherency is maintained, but access latency increases and communication efficiency decreases
Solution Approach 1:
The patent extracts the coherency state information from the traditional copy mechanism and implements a selective update approach. Instead of copying all coherency states from upper-level to lower-level caches, the system only updates the lower-level cache directory entry when the coherency state actually changes, thereby reducing unnecessary access latency while maintaining coherency reliability.
Solution Approach 2:
The lower-level cache directory autonomously determines whether to update its coherency state by comparing incoming coherency information with its current state. This self-service mechanism eliminates the need for mandatory updates from upper-level caches, reducing communication overhead and access latency while ensuring coherency is maintained through selective updates.
2Reliability
If coherency states are copied from upper-level caches to lower-level caches, then cache coherency is maintained, but communication efficiency decreases
Solution Approach 1:
The patent extracts the essential coherency update mechanism from the traditional copy-all-approach, implementing a selective update system that only communicates coherency state changes when necessary. This reduces communication traffic between cache levels while maintaining coherency reliability.
Solution Approach 2:
Instead of performing complete coherency state copying from upper-level to lower-level caches, the system performs partial action by only updating the lower-level cache directory when the coherency state actually changes. This partial update approach significantly improves communication efficiency while sufficient to maintain cache coherency.
3Loss of time
If the Ig state is introduced to indicate global invalidity, then access latency is reduced by allowing exclusive access without retrying, but cache state complexity increases
Solution Approach 1:
The patent introduces a new coherency state parameter (Ig - Invalid globally) to the existing cache state machine. This additional state parameter enables the cache to distinguish between locally invalid and globally invalid data, allowing exclusive access requests to proceed without retrying when the data is globally invalid, thereby reducing access latency despite the increased state complexity.
Data Source
AI summary
A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.