L3 Cache Partitioning for QoS Isolation

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Solution Overview

Problem

In data centers, the imbalance in Quality of Service (QoS) requirements among applications and shared resources in level 3 (L3) caches leads to inefficient processor utilization, as applications with higher QoS requirements cannot be run efficiently on compute units already running lower QoS applications due to resource sharing.

Innovation Solution

The L3 cache is partitioned into subcaches, with each compute unit allocated specific subcaches based on QoS requirements, using a mapping table to manage associations between compute units and subcaches, allowing for efficient scheduling and data storage without interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If applications are run on shared compute units with common L3 cache, then processor utilization increases, but QoS requirements cannot be met due to resource interference

Engineering Contradiction:
Improveprocessor utilizationVSAvoidQoS requirement fulfillment
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The L3 cache is divided into multiple partitioned subcaches, each associated with a specific compute unit. This segmentation allows each compute unit to have dedicated cache space, eliminating interference from other applications while maintaining high processor utilization through shared compute units.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different partitions of the L3 cache are allocated to different compute units based on their specific QoS requirements. High QoS applications receive dedicated cache partitions that guarantee performance, while lower QoS applications share remaining resources, ensuring each application receives appropriate quality of service.

Inventive Principle:
Principle #3Local quality

2Reliability

If L3 cache is partitioned into subcaches for each compute unit, then QoS requirements are met, but cache management complexity increases

Engineering Contradiction:
ImproveQoS requirement fulfillmentVSAvoidcache management
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Each compute unit autonomously manages its own associated subcache partition, making independence decisions without requiring complex centralized cache management. The compute unit itself serves its cache needs, reducing overall system complexity while maintaining QoS guarantees.

Inventive Principle:
Principle #25Self-service

3Productivity

If compute units are shared across multiple applications, then resource efficiency improves, but interference between applications with different QoS occurs

Engineering Contradiction:
Improveresource efficiencyVSAvoidapplication interference
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The L3 cache is segmented into separate partitions for each compute unit, preventing interference between applications running on the same compute unit. Each application accesses only its dedicated cache partition, eliminating harmful interference while maintaining resource sharing at the compute unit level.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The partitioned cache structure acts as an intermediary between compute units and main memory, providing isolation between applications. Each compute unit interacts only with its own cache partition, which mediates access to the broader memory system, preventing direct interference between applications.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS8606999B2Cache partitioning
Publication Date: 2013.12.10 ADVANCED MICRO DEVICES INC
  • US8606999B2 patent drawing
  • US8606999B2 patent drawing
  • US8606999B2 patent drawing

AI summary

A method and apparatus for partitioning a cache includes determining an allocation of a subcache out of a plurality of subcaches within the cache for association with a compute unit out of a plurality of compute units. Data is processed by the compute unit, and the compute unit evicts a line. The evicted line is written to the subcache associated with the compute unit.