L4S Packet ECN Marking via NPU-Assisted Hardware Forwarding

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Solution Overview

Problem

Legacy congestion avoidance mechanisms in network gateways introduce large latency, throughput fluctuation, and bandwidth waste in high-speed environments, and processing ECN marking of Low Latency, Low Loss, Scalable Throughput (L4S) packets by a central processing unit (CPU) occupies CPU resources, degrading overall gateway performance.

Innovation Solution

A network packet processing device utilizing a hardware-accelerated forwarding circuit and a network processing unit (NPU) to perform ECN marking on L4S packets without CPU intervention, incorporating a hardware-accelerated forwarding circuit, NPU, and queue direct memory access (QDMA) system to manage packet forwarding and ECN marking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the CPU is responsible for processing ECN marking of L4S packets, then ECN marking can be performed accurately, but CPU resources are occupied and overall gateway performance degrades

Engineering Contradiction:

ImproveECN marking accuracyVSAvoidgateway performance

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent divides the packet processing function into two segments: the hardware-accelerated forwarding circuit handles L4S packet forwarding and ECN marking, while the CPU handles other control plane functions. This segmentation allows ECN marking to be performed in hardware without occupying CPU resources, resolving the contradiction between marking accuracy and gateway performance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent replaces the software-based ECN marking process (which requires CPU intervention) with a hardware-accelerated marking circuit that performs ECN marking automatically at wire speed. This substitution eliminates the need for CPU resources while maintaining accurate ECN marking capability.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If legacy congestion avoidance mechanisms are used, then packet loss can be detected, but large latency, throughput fluctuation, and bandwidth waste occur in high-speed networks

Engineering Contradiction:

Improvecongestion detection capabilityVSAvoidlatency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements L4S ECN marking that provides preliminary congestion notification before packet loss occurs. The hardware-accelerated marking circuit sets ECN bits in packet headers to alert senders of impending congestion, allowing them to reduce sending rates proactively. This prevents the need to wait for packet loss, thereby reducing latency and avoiding bandwidth waste.

Inventive Principle:

Principle #10Preliminary action

3Speed

If hardware-accelerated forwarding is used for L4S packets, then forwarding speed is improved, but ECN marking capability may be compromised without CPU intervention

Engineering Contradiction:

Improvepacket forwarding speedVSAvoidECN marking capability

Core Design Contradiction:

SpeedVSMeasurement precision

Solution Approach 1:

The patent merges the ECN marking function with the hardware-accelerated forwarding circuit. The marking circuit is integrated into the forwarding path, allowing ECN marking to be performed simultaneously with packet forwarding without requiring separate CPU intervention. This combination maintains wire-speed forwarding while ensuring accurate ECN marking capability.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20260095412A1Network packet processing device with explicit congestion notification marking aided by network processing unit and related network packet processing method

Publication Date: 2026.04.02 AIROHA TECH (SUZHOU) LTD

AI summary

A network packet processing device includes a hardware-accelerated forwarding circuit and a network processing unit (NPU). The hardware-accelerated forwarding circuit is used to receive a plurality of L4S packets from a network port and send the plurality of L4S packets to another network port through hardware-accelerated forwarding without intervention of a central processing unit (CPU). The NPU is used to perform ECN marking on at least a portion of the plurality of L4S packets.