Label Masked Addressable Memory for Low Latency Packet Processing

The patent divides the search space into multiple segments by using a trie data structure where keys are partitioned across different nodes. The search process is segmented into traversing different levels of the trie, allowing parallel search operations to proceed simultaneously through different key segments, thereby reducing overall decision latency while maintaining search capability.

The patent transitions from traditional linear or hierarchical search approaches to a multi-dimensional trie structure where keys can be accessed through multiple paths and levels. This dimensional organization allows the system to exploit spatial locality and enable parallel traversal, reducing decision latency without sacrificing search reliability.

The patent uses a trie data structure that can be implemented using standard memory cells rather than specialized TCAM hardware. The trie nodes and edges are essentially copied representations of key prefixes, organized in a space-efficient manner that leverages conventional memory architecture, significantly reducing the circuit area required compared to TCAM while preserving search capability.

The patent changes the fundamental parameter of how search data is organized and accessed by adopting a trie structure with variable-length key prefixes stored in conventional memory. This parameter change from TCAM's fixed-format matching to trie's hierarchical prefix matching enables the same search functionality with dramatically reduced hardware resources.

The patent implements a dynamic trie structure that can be efficiently scaled and adapted. The trie can dynamically allocate memory for new key prefixes and accommodate varying packet processing requirements. This dynamic organization allows the system to scale from small to large networks while maintaining efficient packet processing performance, unlike static conventional derivation logic.

The trie-based derivation logic serves multiple functions: it performs prefix matching, supports variable-length keys, enables parallel search operations, and can be scaled to different sizes. This universal structure replaces multiple specialized conventional logic units, providing both improved packet processing and enhanced scalability across different network configurations.