Ladder Program Verification Using Counterexample Error Traces
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Solution Overview
Problem
Current methods for debugging Ladder programs in Programmable Logic Controllers (PLCs) are non-exhaustive and time-consuming, often failing to guarantee that all possible executions are tested, and require manual intervention to analyze test outputs, making it difficult to understand and fix errors.
Innovation Solution
A method that translates a Ladder program into a logical framework, determines property violations, generates counter-examples, and simulates error scenarios to provide detailed information on initial and intermediary configurations leading to errors, allowing automated and exhaustive debugging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation method is used for debugging Ladder programs, then manual testing can be performed with simple setup, but the method is non-exhaustive and time-consuming, failing to guarantee coverage of all possible executions
Solution Approach 1:
The patent introduces an intermediary formal model (Time Petri Net) that bridges the Ladder Diagram program and the verification process. This model enables exhaustive analysis of all possible executions through automated model-checking, eliminating the non-exhaustiveness of manual simulation while reducing debugging time through automation.
Solution Approach 2:
The patent replaces the mechanical manual simulation process with an automated formal verification system. Instead of manually setting up and executing test cases, the system automatically translates the Ladder program into a formal model and uses model-checking algorithms to exhaustively verify all possible executions, significantly reducing debugging time while improving reliability.
2Loss of time
If model-checking method is used to execute program model, then CPU time is saved compared to program execution, but execution paths-related complexity is exponential and testing efficiency is still limited
Solution Approach 1:
The patent changes the parameters of the verification system by using Time Petri Net with explicit time constraints and resource management. This parameterization allows the model-checking process to handle industrial-scale programs efficiently by bounding the state space through time and resource constraints, reducing the exponential complexity while maintaining exhaustive verification.
3Ease of operation
If manual test configuration is used, then tests can be developed and run with human insight, but output analysis requires manual intervention and it is hard to understand the fundamental reason of the error
Solution Approach 1:
The patent implements automated feedback mechanisms that provide detailed counter-examples and error traces when property violations are detected. The system automatically analyzes the model execution, identifies the fundamental cause of errors, and presents structured information about initial configurations and execution paths leading to errors, eliminating the need for manual output analysis while improving ease of error understanding.
Solution Approach 2:
The verification system performs self-service by automatically translating Ladder programs into formal models, executing the model-checking process, analyzing results, and generating comprehensive error reports without human intervention. The system independently identifies and explains the fundamental reasons for errors, making the debugging process fully automated while maintaining high ease of error understanding.
4Reliability
If exhaustive verification of all execution configurations is performed, then reliability of program validation is improved, but CPU time and computational resources increase
Solution Approach 1:
The patent applies preliminary action by translating the Ladder program into a formal Time Petri Net model before verification. This preliminary translation establishes a structured representation with explicit time and resource constraints that enables efficient model-checking. The preliminary model construction allows exhaustive verification of all execution configurations to be performed with reduced CPU time consumption compared to direct verification of the original program.
Data Source
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AI summary
It is disclosed a PLC Program analysis method where a program (PROG) is translated (TRANS) into a model (MOD) in a logical framework, from which properties (Prop) are determined. Said properties coupled with user specifications (IntProp) are verified by an automated solver (SMT). If contraposition of a property (Prop) is satisfiable, counter-examples (PROOF NOK) representative of model inputs and internal memory values is provided. Counter-examples (PROOF NOK) are translated into error initial configurations (IniConf) of said model. Execution of the model is simulated (EXE) with said model error initial configurations (IniConf), and error intermediary configurations (AST-IntConf) of said model simulation are recorded up to said property violation. Error initial and intermediary configurations (Lad-IniConf, Lad-IntConf) of said original program (PROG) are derived from error initial configurations (IniConf) of said model and error intermediary configurations (AST-IntConf) of said model simulation and displayed. An apparatus for executing said method is provided.