Ladder STI Structure for LDMOS Breakdown and Speed Balance

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Solution Overview

Problem

As semiconductor devices continue to integrate more components into a given area with reduced minimum feature sizes, challenges arise in preventing high voltage breakdown while maintaining device speed.

Innovation Solution

Implementing a ladder shallow trench isolation (STI) structure with multiple depths under the gate structure of a laterally-diffused metal-oxide semiconductor (LDMOS) device to enhance high voltage breakdown prevention and improve device speed by providing a shorter channel path.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but high voltage breakdown risk increases

Engineering Contradiction:

Improveintegration densityVSAvoidhigh voltage breakdown prevention

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The STI structure is divided into multiple depth sections (first depth section and second depth section) with different depths, creating a segmented isolation structure that provides different levels of protection against high voltage breakdown while accommodating reduced feature sizes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different sections of the STI structure have different depths and properties - the first depth section extends to a first depth while the second depth section extends to a second depth, allowing localized optimization for both high voltage protection and integration density

Inventive Principle:

Principle #3Local quality

2Speed

If the channel length is reduced to improve device speed, then device speed increases, but high voltage breakdown risk increases

Engineering Contradiction:

Improvedevice speedVSAvoidhigh voltage breakdown prevention

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The STI structure transitions from a single-depth planar configuration to a multi-depth vertical configuration, adding a depth dimension that provides high voltage protection without increasing the lateral channel length, thus maintaining device speed

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Reliability

If a deeper STI structure is used to prevent high voltage breakdown, then high voltage performance improves, but device speed decreases due to longer channel path

Engineering Contradiction:

Improvehigh voltage breakdown preventionVSAvoiddevice speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The STI structure is segmented into multiple depth sections where only specific sections extend deeper into the substrate, providing high voltage protection localized to areas where it is most needed, while maintaining shorter channel paths in other areas to preserve device speed

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20260052725A1Shallow trench isolation structures and techniques

Publication Date: 2026.02.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A semiconductor structure is disclosed that includes: a source feature and a drain feature disposed in a substrate; a gate structure disposed above the substrate and between the source feature and the drain feature; and a first ladder shallow trench isolation (STI) feature disposed in the substrate at least partially under the gate structure in a channel region between the source feature and the drain feature, the first ladder STI feature including a plurality of sections of different depths including a first depth section and a second depth section.