Ladder-Shaped Trench Gate Power Semiconductor Device
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Solution Overview
Problem
Trench gate type power semiconductor devices experience instability due to negative gate charging (NGC) and high gate-to-collector capacitance, affecting switching stability and breakdown characteristics in high voltage and high current environments.
Innovation Solution
A power semiconductor device with a ladder-shaped trench and a gate electrode layer structure, featuring a well region, floating region, and a gate insulating layer, where the connectors have a shallower depth and wider width than the lines, reducing electric field stress and gate-collector capacitance, and the floating region extends below the lines to surround the bottom surface of the gate electrode, thereby alleviating the NGC phenomenon.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a trench gate type power semiconductor device is used, then high voltage breakdown characteristics are achieved, but negative gate charging phenomenon occurs and switching stability deteriorates
Solution Approach 1:
The gate electrode layer is divided into a first portion filling the deep lines and a second portion filling the shallow connectors, creating a segmented structure that addresses both breakdown voltage and switching stability requirements simultaneously
Solution Approach 2:
Different portions of the gate electrode layer are given different depths and widths to perform different functions: the first portion (deeper, narrower) provides breakdown voltage, while the second portion (shallower, wider) reduces NGC and improves switching stability
2Strength
If the gate electrode layer is made deeper to improve breakdown voltage, then high voltage characteristics are enhanced, but gate-to-collector capacitance increases and switching stability worsens
Solution Approach 1:
The gate electrode layer is segmented into two portions with different depths: the first portion extends deeper to maintain breakdown voltage, while the second portion is shallower to reduce gate-to-collector capacitance and improve switching stability
Solution Approach 2:
The gate electrode layer parameters are optimized by creating portions with different depths and widths, allowing simultaneous achievement of high breakdown voltage and low gate-to-collector capacitance
Data Source
AI summary
A power semiconductor device includes a semiconductor layer, a ladder-shaped trench recessed a specific depth from a surface of the semiconductor layer into the semiconductor layer and including a pair of lines having a first depth and a plurality of connectors connected between the pair of lines and having a second depth shallower than the first depth, a well region defined in the semiconductor layer between the pair of lines and between the plurality of connectors of the trench, a floating region defined in the semiconductor layer outside the pair of lines of the trench, a gate insulating layer disposed on an inner wall of the trench, and a gate electrode layer disposed on the gate insulating layer to fill the trench and including a first portion in which the pair of lines is filled and a second portion in which the plurality of connectors is filled. A depth of the second portion of the gate electrode layer is shallower than a depth of the first portion of the gate electrode layer.