Laminate Base IC Package with Strip Test for Stacked Die Yield
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Solution Overview
Problem
Current semiconductor package stacking methods result in lower yields due to premature die failures and inefficiencies, particularly in smaller, more complex electronic devices, where increased demands for smaller and more functional products are not adequately met by existing packaging solutions.
Innovation Solution
An integrated circuit package system utilizing a laminate base with a substrate, an integrated circuit, and a molded cover, along with a strip test for verification, allows for the stacking and electrical connection of bare dies, ensuring each package is tested and verified before further assembly, thereby improving yield and reducing package height.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple dies are stacked in a single package to reduce size, then package volume is reduced, but manufacturing yield decreases due to premature die failures
Solution Approach 1:
The patent implements preliminary testing of the base package before stacking additional dies on top. The base package is fully tested and verified to be functional before the second die is mounted, ensuring that any failures are detected early rather than after complete assembly. This preliminary action prevents wasting time and resources on packages with defective base components.
Solution Approach 2:
The patent divides the packaging process into distinct segments: first packaging and testing the base package separately, then separately packaging the second die, and finally assembling them together. This segmentation allows independent verification of each component's functionality before combination, improving overall yield by identifying failures at intermediate stages rather than at the final product level.
2Device complexity
If dies are stacked without intermediate testing to reduce manufacturing complexity, then device complexity is reduced, but reliability decreases due to undetected failures
Solution Approach 1:
The patent performs preliminary testing of the base package at an intermediate stage before final assembly. This preliminary action catches failures early in the manufacturing process, preventing defective packages from proceeding to later stages. The testing includes verifying electrical functionality and ensuring the base package meets specifications before the second die is attached.
Solution Approach 2:
The patent implements a feedback mechanism where test results from the base package determine whether to proceed with stacking the second die. If the base package fails testing, the process stops and the defective package is discarded or reworked. This feedback loop ensures that only qualified base packages advance to the next manufacturing stage, maintaining high reliability.
3Ease of manufacture
If complete package assembly is performed before testing to simplify manufacturing steps, then ease of manufacture is improved, but loss of time increases due to rework of failed packages
Solution Approach 1:
The patent performs preliminary testing of the base package before completing the full assembly with the second die. This preliminary action identifies failures early, preventing time-consuming rework of completely assembled packages. By testing at an intermediate stage, the manufacturer avoids the inefficiency of discovering defects only after all assembly steps are completed.
Solution Approach 2:
The patent skips the final assembly step for base packages that fail preliminary testing. Instead of completing the full assembly process for potentially defective packages, the manufacturing process rushes through to test early, identifies failures, and discards or reworks only the base package portion, saving significant time compared to discovering failures after complete assembly.
Data Source
AI summary
An integrated circuit package system with laminate base includes: a base package including: a laminate substrate strip, an integrated circuit on the laminate substrate strip, a molded cover over the integrated circuit and the laminate substrate strip, and a strip test of the base package; a bare die on the base package; the bare die electrically connected to the laminate substrate strip; and the bare die and the base package encapsulated.