Laminate Electronic Device Bond Layer Thickness Control

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Solution Overview

Problem

Existing methods for embedding semiconductor components into laminate substrates, such as printed circuit boards, face challenges in achieving low production costs, efficient electrical connections, and high versatility in circuit design and routing, while also requiring minimal size, thickness, and weight, particularly in portable electronic devices.

Innovation Solution

The method involves mounting semiconductor chips on a carrier with a bond layer, such as diffusion solder or conductive adhesives, and embedding them in an electrically insulating layer, allowing for precise control of bond layer thickness and efficient heat transfer, using techniques like sputtering or nano-paste application to create a thin, reliable connection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Weight of moving object

If semiconductor chips are directly embedded into PCBs and SBU laminate substrates, then size and weight are minimized, but production cost increases and manufacturing complexity increases

Engineering Contradiction:
Improveweight of electronic deviceVSAvoidproduction cost
Core Design Contradiction:
Weight of moving objectVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by pre-mounting semiconductor chips on a carrier substrate before embedding them into the laminate substrate. This preliminary mounting on a separate carrier allows for standardized processing and easier replacement, reducing overall manufacturing complexity and cost while achieving miniaturization goals.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the embedding process by using a separate carrier substrate that holds multiple semiconductor chips. This carrier is then embedded as a unit into the laminate substrate, dividing the complex embedding task into manageable stages and improving manufacturability.

Inventive Principle:
Principle #1Segmentation

2Length of stationary object

If bond layer thickness is reduced to achieve smaller device size, then thickness is minimized, but electrical connection reliability deteriorates

Engineering Contradiction:
Improvethickness of deviceVSAvoidelectrical connection reliability
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The patent uses composite materials for the bond layer, combining conductive adhesives with metallic particles or using diffusion solder that creates intermetallic compounds. These composite structures provide both thin profile and reliable electrical connection through enhanced adhesion and conductive pathways.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent changes the material parameters of the bond layer by using diffusion soldering processes that create controlled intermetallic compound formations. This allows achieving reliable electrical connections at reduced thickness through optimized material composition and bonding parameters.

Inventive Principle:
Principle #35Parameter changes

3Adaptability or versatility

If multiple semiconductor chips are embedded to achieve versatile circuit design, then circuit functionality is improved, but device complexity increases

Engineering Contradiction:
Improvecircuit design versatilityVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent creates a universal carrier substrate that can accommodate various types of semiconductor chips through standardized mounting procedures. This universal approach allows different chip combinations to achieve versatile circuit designs while maintaining a consistent, manageable device structure that reduces overall complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Ease of manufacture

If conventional embedding methods are used, then manufacturing process is simple, but heat removal efficiency deteriorates

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidheat removal efficiency
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent introduces a specialized bond layer as an intermediary between the semiconductor chips and the carrier substrate. This bond layer is designed with enhanced thermal conductivity properties, acting as an efficient heat transfer medium that maintains manufacturing simplicity while significantly improving heat removal efficiency from the embedded chips.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the production of laminate electronic devices with high yield and reliability, achieving a small and constant thickness, efficient heat removal, and versatile circuit designs, suitable for applications like power supplies and DC-DC converters.

Implementation Method 1

efficient heat transfer

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

using techniques like sputtering or nano-paste application

Methodology Applied
Scientific EffectSputtering: Sputtering

Data Source

PatentUS8698298B2Laminate electronic device
Publication Date: 2014.04.15 INFINEON TECHNOLOGIES AG
  • US8698298B2 patent drawing
  • US8698298B2 patent drawing
  • US8698298B2 patent drawing

AI summary

A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 μm. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip.