Laminate Low-k Spacer Liner for Metal Gate Height Variability
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Solution Overview
Problem
Low-k spacer damage during post poly pull cleaning processes in replacement gate processes leads to taper profiles and increased metal gate height variability, preventing the implementation of lower-k spacers for enhanced device performance.
Innovation Solution
A laminate low-k dielectric liner composed of alternating materials is used on the sidewall of a replacement metal gate structure, with a low-k dielectric spacer deposited directly on the laminate liner, forming a robust spacer profile that reduces downstream process variability and metal gate height variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If low-k materials are used as sidewall spacer to boost device performance, then device performance is improved, but the low-k spacer is damaged during post poly pull cleaning processes resulting in taper profile and metal gate height variability
Solution Approach 1:
The patent applies composite materials by creating a laminate liner structure consisting of multiple alternating layers of low-k dielectric material and sacrificial material. This composite structure allows the low-k material to provide the desired electrical performance while the sacrificial layers protect it from damage during cleaning processes, resolving the contradiction between performance improvement and reliability maintenance
Solution Approach 2:
The sacrificial material layers act as intermediaries between the low-k dielectric material and the cleaning chemicals. These intermediary layers are selectively removed during post poly pull cleaning, protecting the low-k spacer from direct exposure to damaging chemicals while still allowing the low-k material to function as intended for device performance enhancement
2Productivity
If low-k spacer is used to enhance device performance, then device performance is boosted, but metal gate height variability and source/drain contact shorts increase
Solution Approach 1:
The laminate liner with alternating low-k dielectric and sacrificial material layers provides a protective composite structure that maintains spacer profile integrity during manufacturing. This prevents the tapering that would otherwise cause metal gate height variability, while still allowing the low-k material to deliver the desired device performance enhancement
Solution Approach 2:
The sacrificial material layers are deposited beforehand to cushion and protect the low-k dielectric material from damage during subsequent cleaning processes. This prior protection prevents profile degradation that would lead to manufacturing precision issues, while the low-k material continues to provide performance benefits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a significant reduction in metal gate height variability and source/drain contact shorts, enabling the use of weaker materials with lower-k values as sidewall spacers, thus boosting device performance and reducing downstream process variability.
Implementation Method 1
depositing a laminate low-k dielectric liner composed of alternating materials on the dummy gate structure
Implementation Method 2
depositing a laminate low-k dielectric liner composed of alternating materials on the dummy gate structure
Implementation Method 3
depositing a low-k dielectric spacer on the laminate low-k dielectric liner
Implementation Method 4
depositing a low-k dielectric spacer on the laminate low-k dielectric liner
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to a spacer with laminate liner and methods of manufacture. The structure includes: a replacement metal gate structure; a laminate low-k liner on the replacement metal gate structure; and a spacer on the laminate low-k liner.