Low Inductance Power Module Package Design
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Solution Overview
Problem
Existing power switching module assemblies face challenges in minimizing parasitic inductance, which leads to power system losses and affects the electrical, thermal, and mechanical capabilities of power semiconductor devices.
Innovation Solution
The power module design features a commutation power loop with conductive substrates and wire bonds that are ultrasonically welded or soldered to minimize inductance by maintaining current paths in close proximity, canceling out induced electromagnetic fields and using a laminated bus structure to reduce wire bond lengths and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If wire, ribbon, or planar interconnect bonding is used to connect semiconductor devices to copper traces on DBC substrates, then electrical connection is achieved, but parasitic inductance increases leading to power system losses
Solution Approach 1:
The patent transitions from planar 2D trace routing to a 3D laminated bus bar structure with multiple stacked conductive layers. This dimensional change allows current paths to be routed through adjacent layers with minimal separation distance, dramatically reducing loop area and parasitic inductance while maintaining electrical connection functionality.
Solution Approach 2:
The patent merges multiple conductive layers into a single integrated laminated bus bar assembly where copper traces on different substrate layers are electrically connected through vertical vias. This combining of separate current paths into a unified low-inductance structure reduces overall parasitic inductance and power system losses.
2Productivity
If copper traces are routed on insulating substrates with wire or ribbon bonding, then device interconnection is achieved, but circuit inductance increases reducing efficiency
Solution Approach 1:
The invention moves from single-layer planar routing to multi-layer 3D laminated construction where conductive traces are stacked vertically with minimal spacing. This dimensional transformation creates tightly coupled current loops that minimize inductance, thereby improving power conversion efficiency.
Solution Approach 2:
The patent changes the geometric parameters of the current path by reducing the loop area through adjacent layer routing and minimizing trace separation distances. This parameter optimization directly reduces circuit inductance and improves overall power conversion efficiency.
3Ease of operation
If traditional planar metal traces are used on ceramic substrates, then signal routing is achieved, but the current paths require adjacent traces on a planar surface increasing inductance
Solution Approach 1:
The patent replaces traditional planar 2D trace routing with 3D laminated bus bar construction where multiple conductive layers are stacked vertically. This allows current paths to route through adjacent layers with minimal separation, maintaining signal routing capability while dramatically reducing parasitic inductance through reduced loop area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves 30%-70% lower parasitic inductance compared to traditional designs, enhancing performance at high frequencies and improving efficiency by reducing impedance and power losses.
Implementation Method 1
conductive substrates and wire bonds that are ultrasonically welded or soldered to minimize inductance
Implementation Method 2
maintaining current paths in close proximity, canceling out induced electromagnetic fields
Data Source
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AI summary
A method and system for a power module is provided. The power module includes a first substrate (102) including a first conductive substrate (114) having a first plurality of power semiconductor switches (122) arranged thereon, and at least one second conductive substrate (116) electrically coupled to the first conductive substrate. A first terminal (108) is electrically coupled to the first conductive substrate. The power module also includes a second substrate (110) including a third conductive substrate (130) having a second plurality of power semiconductor switches (136) arranged thereon, and at least one fourth conductive substrate (132) electrically coupled to the third conductive substrate. The third conductive substrate is electrically coupled to the second conductive substrate. A second terminal (112) is electrically coupled to the fourth conductive substrate.