Laminated Chip Capacitor Asymmetric Cover Layers Noise Reduction
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Solution Overview
Problem
Existing laminated chip electronic components generate significant acoustic noise due to vibrations when mounted on printed circuit boards, and existing solutions do not adequately address this issue, particularly in reducing noise levels when internal electrodes are parallel to the PCB.
Innovation Solution
A laminated chip capacitor design with a thicker lower cover layer than upper cover layer, additional electrode layers within the lower cover layer, and specific thickness ratios to minimize strain differences, allowing for reduced acoustic noise by controlling the central portion deviation and electrode layer configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the lower cover layer is made thicker than the upper cover layer with specific thickness ratios, then acoustic noise is reduced by minimizing strain differences, but the device structure becomes more complex
Solution Approach 1:
The patent applies asymmetry by making the lower cover layer thicker than the upper cover layer. Specifically, the lower cover layer has a thickness of 10-20 μm while the upper cover layer has a thickness of 5-15 μm. This asymmetric design creates different strain characteristics in the lower and upper portions of the capacitor, which helps minimize strain differences during voltage application and reduces acoustic noise generated by vibrations.
Solution Approach 2:
The patent applies local quality by adding an additional electrode layer specifically within the lower cover layer region, rather than uniformly distributing electrodes throughout. This localized structural modification allows the lower cover layer to have different mechanical and electrical properties compared to the upper cover layer, enabling targeted strain management and noise reduction in the critical lower region where vibrations are most problematic.
2Object-affected harmful factors
If additional electrode layers are added within the lower cover layer, then strain distribution is improved and acoustic noise is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the electrode structure into multiple distinct layers: internal electrodes within the active layer, external electrodes on the surface, and additional electrode layers embedded within the lower cover layer. This segmented approach allows each electrode type to be formed through specialized processes optimized for its specific function and location, improving overall strain distribution and acoustic noise reduction while maintaining manufacturing feasibility through modular fabrication steps.
3Object-affected harmful factors
If the central portion of the active layer is deviated from the central portion of the ceramic body, then vibration patterns are optimized to reduce noise, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary anti-action by proactively designing the active layer to be intentionally offset from the ceramic body center during the manufacturing planning stage. The active layer central portion is positioned at a distance of 5-15 μm from the ceramic body central portion, which pre-compensates for vibration-induced acoustic noise. This preliminary structural arrangement ensures that during voltage application, the strain distribution and vibration patterns are optimized to minimize noise generation, counteracting the potential harmful effects before they occur during operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces acoustic noise levels by managing strain and displacement within the capacitor, preventing delamination and crack formation, and maintaining effective capacitance, even with varying electrode pad sizes.
Implementation Method 1
When DC or AC voltages are applied to the multilayer capacitor having internal electrodes overlapping with dielectric layers interposed therebetween, a piezoelectric effect takes place between the internal electrodes, generating vibrations.
Data Source
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AI summary
A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; first and second external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer; and additional electrode layers disposed irrespective of a formation of capacitance within the lower cover layer.