Laminated Chip Device Via Insulation
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Solution Overview
Problem
Laminated chip devices face issues with stress accumulation and deformation at through-hole overlaps, leading to short circuits, leakage currents, and transient currents due to improper implementation of designed characteristics.
Innovation Solution
Incorporating a non-conductive region in the internal electrode patterns of the laminated chip device, specifically designed to prevent stress-induced deformations by ensuring insulation between vias and common electrode patterns, thereby maintaining electrical characteristics and preventing short circuits and leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-holes are formed to penetrate each sheet to connect conductor patterns vertically, then electrical connection between layers is achieved, but stress accumulates at through-hole overlap regions causing conductor deformation and short circuits
Solution Approach 1:
The harmful conductor material is extracted or removed from the overlap region of through-holes. The patent specifies that when through-holes overlap, the conductor filling the through-hole should not extend into the overlap region, effectively removing the potential short-circuit path while maintaining electrical connection functionality through alternative routing.
Solution Approach 2:
The conductor pattern is segmented to avoid continuous conduction through the through-hole overlap region. The conductor is divided into separate segments that terminate before the overlap region, preventing stress-induced deformation from causing short circuits while maintaining necessary electrical connections through other paths.
2Volume of moving object
If multiple sheets are laminated and compressed to form the chip, then miniaturization and high integration are achieved, but stress accumulates in through-hole regions causing deformation and malfunction
Solution Approach 1:
The conductor material is extracted from the through-hole overlap region to eliminate the source of deformation-induced positioning errors. This ensures that even under lamination compression, the conductor maintains its designed position and distance from adjacent conductors, preserving manufacturing precision.
3Reliability
If through-holes are filled with conductor to connect patterns vertically, then electrical conductivity is improved, but stress causes conductor deformation leading to short circuits and leakage currents
Solution Approach 1:
The conductor is removed from the through-hole overlap region where stress concentration occurs during lamination. This extraction prevents the conductor deformation that would otherwise create short circuits and leakage currents, while electrical conductivity is maintained through properly positioned conductors in non-overlap regions.
Solution Approach 2:
The continuous conductor path is segmented to terminate before the through-hole overlap region. This segmentation prevents stress-induced deformation from creating unwanted conduction paths, eliminating short circuits and leakage currents while maintaining necessary electrical connectivity through alternative routes.
Data Source
AI summary
Provided is a laminated chip device including a first laminate in which a plurality of conductor patterns formed on a plurality of sheets are connected to each other through a via formed to penetrate at least a sheet, and a second laminate provided over or below the first laminate and having a plurality of internal electrode patterns formed on a plurality of sheets, and the internal electrode patterns have a non-conductive region in at least a portion of an area corresponding to the via.