Laminated Ferroelectric Capacitor Integrated Circuit Layout
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Solution Overview
Problem
Conventional integrated circuits, such as memory devices and RFID tags, face challenges in minimizing layout area due to separate regions for capacitor and peripheral circuits, leading to increased overall layout area and power noise, as capacitors are formed at the same process level as the circuit, preventing lamination and necessitating larger chip sizes.
Innovation Solution
The integration of a ferroelectric capacitor region on top of the cell array and peripheral circuit regions, utilizing ferroelectric capacitors with higher dielectric constants, allowing for lamination and reducing the overall layout area by sharing process levels and forming capacitors in a lamination type structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If capacitors and peripheral circuits are formed in separate regions on the same layer, then each region can be independently designed, but the overall layout area increases
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional lamination by forming the capacitor region on a different layer (upper or lower layer) than the peripheral circuit region. This vertical stacking approach allows both regions to occupy the same horizontal footprint while being electrically isolated through different process levels, thereby reducing the overall layout area without compromising independent design capability
Solution Approach 2:
The capacitor region is embedded within the same horizontal footprint as the peripheral circuit region by using lamination. The capacitor structure is formed in upper or lower layers that overlay the peripheral circuit region, effectively nesting one functional region within the spatial envelope of another, thus minimizing the total chip area
2Ease of manufacture
If MOS capacitor or PIP or MIM capacitor is used in peripheral circuit region, then the capacitor can be formed at the same process level as the circuit, but the capacitor region and peripheral circuit region cannot be laminated
Solution Approach 1:
The patent resolves the lamination limitation by moving the capacitor formation to a different vertical layer. The capacitor region is formed in upper or lower layers relative to the peripheral circuit region, enabling lamination while maintaining compatibility with standard semiconductor fabrication processes through sequential layer formation
3Ease of manufacture
If conventional capacitor structures are used, then the manufacturing process is simple, but the dielectric constant is reduced requiring increased capacitor area
Solution Approach 1:
The patent employs a composite capacitor structure with a dielectric layer having a dielectric constant of 5 or more. This high-k dielectric material is integrated into the existing manufacturing process flow, combining the simplicity of conventional capacitor fabrication with enhanced electrical performance that reduces the required capacitor area for a given capacitance value
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maximizes the capacitor region without increasing the layout area, reduces power noise, and achieves high-speed operation by using large capacitance ferroelectric capacitors, thereby minimizing chip size and production costs.
Implementation Method 1
FeRAM, which is a memory device almost identical in structure to DRAM, uses high remanent polarization which is a characteristic of a ferroelectric by employing the ferroelectric as a capacitor material. Even if an electric field is removed, data is not erased due to remanent polarization.
Implementation Method 2
In the case that the insulator is a paraelectric, a dielectric constant is reduced to relatively increase an area of the capacitor. This approach maximizes an area of a capacitance capacitor without increasing a layout area.
Data Source
AI summary
An integrated circuit and a manufacturing method thereof are provided. A chip size can be reduced by forming a memory device in which a ferroelectric capacitor region is laminated on a DRAM. The integrated circuit includes a cell array region having a capacitor, a peripheral circuit region, and a ferroelectric capacitor region being formed on an upper layer of the cell array region and the peripheral circuit region, and having a ferroelectric capacitor device.