Laminated Gate Electrode for Semiconductor Memory Devices
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Solution Overview
Problem
Conventional semiconductor memory devices with three-dimensionally disposed memory cells require multiple critical photo-etching processes, leading to increased costs and manufacturing complexity, particularly in achieving precise control over source/drain diffusion layers and gate overlap in cylindrical-structure transistors.
Innovation Solution
A semiconductor device with a gate electrode composed of a laminate of multiple conductive films having different work functions, including an n+ type lower-layer electrode, interfacial nitride films, and p+ type intermediate and upper-layer electrodes, which improves the control over the gate overlap and impurity concentration, reducing manufacturing variability and increasing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photo-etching processes are used for cylindrical-structure transistors, then manufacturing process can be implemented, but manufacturing precision of source/drain diffusion layers and gate overlap deteriorates
Solution Approach 1:
The gate electrode is segmented into multiple layers (first gate electrode layer, second gate electrode layer, third gate electrode layer) with different work functions. This segmentation allows independent optimization of each layer's properties to achieve precise control over threshold voltage and gate overlap without requiring multiple critical photo-etching processes, thereby improving manufacturing precision while reducing process complexity.
Solution Approach 2:
Different regions of the gate electrode structure are assigned different local qualities through the use of materials with different work functions. The first gate electrode layer (e.g., tungsten) provides one electrical characteristic, while the second (e.g., molybdenum) and third (e.g., tungsten again) layers provide different characteristics. This local quality differentiation enables precise control of gate overlap and diffusion layer profiles without increasing device complexity.
2Quantity of substance
If high-acceleration ion implantation is used to form source/drain impurity regions at deep points, then impurity concentration can be increased, but process time increases reducing manufacturing throughput
Solution Approach 1:
The gate electrode layers are formed in advance with predetermined work function characteristics before source/drain impurity formation. This preliminary action allows the subsequent ion implantation process to be optimized for both depth and concentration without requiring excessively high acceleration times, as the gate structure is already in place to define the precise implantation parameters needed.
Solution Approach 2:
The invention changes the parameter of gate electrode work function by using multiple layers with different materials (tungsten, molybdenum, etc.). This parameter change enables precise control of the electric field distribution during ion implantation, allowing high impurity concentration to be achieved at deep points without requiring prolonged high-acceleration implantation, thus maintaining high manufacturing throughput.
3Ease of manufacture
If thermal processing is used for impurity diffusion, then source/drain regions can be formed, but gate overlap amount and LDD structure optimization becomes difficult
Solution Approach 1:
The gate electrode is constructed as a composite structure with multiple layers of different conductive materials (e.g., tungsten, molybdenum, tantalum) with different work functions. This composite material approach allows the gate structure to provide precise electric field control during thermal processing, enabling both easy manufacture through standard thermal diffusion and precise control of gate overlap amount and LDD structure formation.
Data Source
AI summary
The semiconductor device includes a substrate having a conductive layer formed on its surface. The conductive layer has a columnar semiconductor formed thereon. The columnar semiconductor has an insulating layer formed therearound. The insulating layer has an electrode film formed therearound. The electrode film functions as an gate electrode of a transistor. The electrode film includes an laminate of two or more conductive films having different work functions.