Laminated Gate Electrode for Reduced PN Isolation Width
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Solution Overview
Problem
The challenge in reducing the separation distance between P-well and N-well in semiconductor devices, such as DRAMs, is hindered by the thickness of gate electrode films, making it difficult to minimize the PN isolation width and thereby limit the reduction of chip size and cost.
Innovation Solution
The semiconductor device design involves forming gate electrodes with laminated films, where the first and second conductive films and insulating films are processed in different steps, allowing for closer proximity of P-channel and N-channel MOSFET gate electrodes by optimizing the work functions and materials, and sharing some layers in the same process steps to reduce the overall distance between them.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate electrodes of P-channel MOSFETs and N-channel MOSFETs are formed in different process steps with thick laminated films, then the performance of MOSFETs is improved, but the separation distance between P-well and N-well cannot be reduced further
Solution Approach 1:
The patent applies preliminary action by forming a first conductive film and first insulating film layer before forming the second conductive film and second insulating film layer. This sequential formation allows the gate electrodes to be positioned closer together than the total thickness of all films, because the first layer serves as a preliminary structure that enables subsequent closer positioning of the second layer.
Solution Approach 2:
The patent transitions from a single-layer gate electrode structure to a multi-layer laminated structure, utilizing the vertical dimension (film stacking) to achieve the required film thickness while allowing horizontal compression (reduced PN isolation width). The gate electrode thickness is distributed across multiple layers in the vertical dimension, enabling reduced spacing in the horizontal dimension.
2Reliability
If the thickness of gate electrode films is increased to improve MOSFET performance, then device reliability is improved, but chip size cannot be reduced
Solution Approach 1:
The patent resolves this contradiction by moving the film thickness requirement to the vertical dimension through laminated multi-layer structure. The total thickness of conductive and insulating films is achieved through stacking (vertical dimension), which enables reduction of the horizontal footprint (chip area) while maintaining the required film thickness for MOSFET performance.
Solution Approach 2:
The patent uses thin film technology to create a laminated structure where multiple thin layers (conductive and insulating films) are stacked to achieve the required total thickness. This thin-film approach allows compact horizontal spacing while maintaining adequate vertical thickness for device performance.
3Area of stationary object
If PN isolation width is reduced to decrease chip size, then manufacturing cost is reduced, but gate electrode formation becomes more difficult
Solution Approach 1:
The patent simplifies manufacturing by forming the first conductive film and first insulating film layer as a preliminary structure before forming the second conductive film and second insulating film layer. This preliminary action creates a structured foundation that guides subsequent film formation, making the complex multi-layer gate electrode structure easier to manufacture even with reduced PN isolation width.
Solution Approach 2:
The patent segments the gate electrode structure into multiple independent layers (first conductive film, first insulating film, second conductive film, second insulating film) that can be formed in separate process steps. This segmentation allows each layer to be optimized and formed independently, simplifying the manufacturing process despite the reduced overall spacing requirement.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate; and a multilevel wiring structure over the semiconductor substrate, the multilevel wiring structure including a first insulating layer, a first conductive layer on the first insulating layer, a second conductive layer on the first insulating layer, a third conductive layer on the first and second conductive layer, a fourth conductive layer on the third conductive layer, and a second insulating layer on the fourth conductive layer. The multilevel wiring structure includes: a first gate electrode comprising first and second insulating films in the first and second insulating layers, respectively, and first, third and fourth conductive films in the first, third and fourth conductive layers, respectively; and a second gate electrode comprising first and second insulating films in the first and second insulating layers, respectively, and second, third and fourth conductive films in the second, third and fourth conductive layers, respectively.