Laminated Metal Lead Structure for Power Module Bond Reliability
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Solution Overview
Problem
Conventional semiconductor power modules face challenges with bonding reliability due to thermal stress and high thermal resistance, particularly with the use of thick copper substrates and Pb-free solder, which can lead to device failure and reduced power cycle capabilities.
Innovation Solution
A power semiconductor apparatus with a plate-shaped thick copper substrate, a conductive bonding layer, and external connection terminals, where the Vickers hardness of the copper substrate is reduced through annealing, and a metallic laminated structure for the metal lead to mitigate thermal stress and improve bonding reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If thick copper substrates are used to reduce thermal resistance, then thermal resistance is reduced, but undue stress is given to the bonded portion of bonding materials causing degradation and reliability concerns
Solution Approach 1:
The patent changes the physical-chemical parameter of the copper substrate by controlling its hardness to be 80 HV or less through annealing treatment. This parameter modification allows the copper substrate to maintain low thermal resistance while having reduced hardness that minimizes stress on bonding materials, thereby resolving the contradiction between thermal performance and bonding reliability
Solution Approach 2:
The patent applies different hardness characteristics to different regions of the copper substrate. The substrate is designed with a hardness gradient or localized soft regions that provide stress relief at bonding interfaces while maintaining structural integrity and thermal conductivity in other areas, thus achieving both low thermal resistance and high bonding reliability
2Duration of action of stationary object
If copper wires are used instead of aluminum wires to prolong lifetime, then lifetime is extended, but the power of ultrasonic waves becomes extremely larger causing devices to be broken
Solution Approach 1:
The patent changes the physical parameter of the copper substrate by annealing it to achieve a hardness of 80 HV or less. This softened state reduces the copper's resistance to ultrasonic bonding, allowing standard ultrasonic wave powers to bond copper wires without causing device damage, thus enabling the use of copper wires for extended lifetime while maintaining device integrity during the bonding process
3Ease of manufacture
If Pb-free solder is used as bonding materials with upper wirings, then bonding is achieved, but the melting point becomes up to approximately the junction temperature causing power cycle capability to decrease
Solution Approach 1:
The patent introduces a soft copper substrate (hardness 80 HV or less) as an intermediary between the Pb-free solder and the bonding interface. This softened copper substrate acts as a stress-absorbing layer that protects the solder joint from thermal stress during power cycling, thereby maintaining bonding ease while significantly improving power cycle capability and overall reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances bonding reliability and reduces thermal resistance, extending the power cycle capability and improving the reliability of the semiconductor device under repeated cooling and heating cycles.
Implementation Method 1
making such a substrate portion as a thick copper substrate has progressed in order to reduce a thermal resistance
Implementation Method 2
the Vickers hardness of the copper substrate is reduced through annealing
Data Source
AI summary
The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10−6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.