Laminated Polymer Substructures for Photosensing Arrays
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Solution Overview
Problem
Existing layered structures produced by lamination often suffer from defects such as pin-holes due to material deposition issues, particularly when one polymer is deposited over another or when a top metal layer is deposited on a polymer material, leading to inefficiencies in the fabrication of electronic devices like photosensing arrays.
Innovation Solution
The proposed solution involves a lamination technique that uses polymer-containing layers, where the surfaces of substructures are moved to meet and attach, forming an interface surface, and the polymer layers are structured to generate free charge carriers or transport charge carriers in response to light or electric fields, reducing pin-hole defects and improving the integrity of the layered structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If material deposition is used to form layered structures, then device integration is achieved, but pin-hole defects occur reducing structure integrity
Solution Approach 1:
A polymer-containing layer is introduced as an intermediary between the first substructure and second substructure during lamination. This polymer layer acts as a mediator that fills gaps and defects, preventing pin-hole formation while enabling successful attachment of the layered structures. The polymer material is deposited on one surface before lamination, creating a defect-tolerant interface that maintains structure integrity.
2Ease of manufacture
If polymer layers are deposited over each other, then layered structure formation is enabled, but pin-hole defects reduce efficiency
Solution Approach 1:
The polymer-containing layer changes the physical and chemical parameters of the deposition interface. By modifying the surface properties with polymer material, the subsequent deposition process achieves better coverage and adhesion, reducing pin-hole defects. The polymer layer alters wetting, adhesion, and filling characteristics to improve manufacturing precision.
3Ease of manufacture
If metal layers are deposited on polymer materials, then electrical functionality is achieved, but pin-hole defects occur
Solution Approach 1:
The polymer-containing layer is deposited in advance on the substrate surface before metal layer deposition. This preliminary polymer layer creates a defect-free foundation that prevents pin-hole formation during subsequent metal deposition. The pre-formed polymer layer ensures continuous coverage and proper adhesion, maintaining attachment integrity while enabling electrical functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces pin-hole defects and enhances the performance of layered structures, particularly in light-interactive devices like photosensing arrays, by ensuring robust attachment and efficient charge transport, as demonstrated by satisfactory photoresponse and reduced dark current in test samples.
Implementation Method 1
the polymer-containing layer is structured so that free charge carriers can be generated in it or charge carriers can be transported through it
Implementation Method 2
the polymer layers are structured to generate free charge carriers or transport charge carriers in response to light or electric fields
Implementation Method 3
a lamination technique that uses polymer-containing layers, where the surfaces of substructures are moved to meet and attach, forming an interface surface
Data Source
AI summary
A layered structure can include laminated first and second substructures and an array with cell regions. The first substructure can include layered active circuitry, the second a top electrode layer. One or both substructure's surface that contacts the other can be on a polymer-containing layer, structured to generate free charge carriers and/or to transport charge carriers. A cell region of the array can include portions of each substructure; the cell region's portion of the first substructure can include a subregion of electrically conductive material and a subregion of semiconductive material, its portion of the second can include part of the top electrode layer. The layered structure can include one or more lamination artifacts on or in the polymer-containing layer; the lamination artifacts can include artifacts of contact pressure, or heat, or of surface shape, and the interface surface can be without vias.