Laminated Semiconductor Arrangement With Laterally Segmented Carriers
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Solution Overview
Problem
The handling and integration of thin, bare power semiconductor dies with a vertical transistor structure in laminated semiconductor devices are challenging due to their fragility and difficulty in fabrication, particularly in achieving improved electrical and thermal characteristics while maintaining a high level of integration.
Innovation Solution
A semiconductor arrangement comprising a leadframe with laterally arranged carriers and semiconductor dies, where an independent interconnection mechanically fixes and electrically insulates the carriers, keeping the semiconductor dies partially exposed and not encapsulated or laminated, allowing for improved mechanical support and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor dies are made thin to improve integration level, then the level of integration is improved, but the ease of handling and manufacturing precision deteriorates
Solution Approach 1:
The patent divides the support structure into multiple carrier regions (first carrier, second carrier) that are laterally arranged and independently support individual semiconductor dies. This segmentation allows each thin die to be supported on its own carrier, improving handling ease without compromising integration level.
Solution Approach 2:
The patent introduces carriers as intermediary structures between the thin semiconductor dies and the external environment. These carriers provide mechanical support and facilitate handling, acting as mediators that protect the fragile thin dies during manufacturing and assembly processes.
2Adaptability or versatility
If multiple semiconductor dies are embedded in a laminated body to improve integration, then the level of integration is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent segments the embedding process by providing separate carrier regions for each semiconductor die, with laterally arranged carriers that simplify the assembly process. This segmentation reduces manufacturing complexity compared to traditional laminated bodies where multiple dies are embedded in a single encapsulating structure.
Solution Approach 2:
The patent transitions from vertical stacking (traditional laminated structure) to lateral arrangement of carriers. By arranging carriers side-by-side in the lateral dimension rather than stacking them vertically, the patent simplifies the manufacturing process while maintaining high integration levels.
3Reliability
If semiconductor dies are encapsulated or laminated to protect them, then reliability is improved, but the ease of handling and testing deteriorates
Solution Approach 1:
The patent applies partial encapsulation by providing carrier regions that support the semiconductor dies without completely enclosing them. This partial action provides sufficient protection for reliability while leaving the dies accessible for handling and testing, avoiding the drawbacks of full encapsulation.
Solution Approach 2:
The patent implements local protection by providing carriers that support specific regions of the semiconductor dies rather than uniform encapsulation. This local quality approach protects the dies where needed for reliability while maintaining accessibility in other areas for handling and testing.
Data Source
AI summary
A semiconductor arrangement comprises a leadframe comprising at least a first and a second carrier, the first and second carriers being arranged laterally besides each other, at least a first and a second semiconductor die, the first semiconductor die being arranged on and electrically coupled to the first carrier and the second semiconductor die being arranged on and electrically coupled to the second carrier, and an interconnection configured to mechanically fix the first carrier to the second carrier and to electrically insulate the first carrier from the second carrier, wherein the first and second semiconductor dies are at least partially exposed to the outside.