Laminated Semiconductor Package Thermal Separation
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Solution Overview
Problem
Laminated semiconductor packages face challenges in reducing the reliability issues due to thermal radiation from logic devices and supporting semiconductor chips with multiple pins, as existing structures struggle to efficiently manage heat and accommodate high-pin-count chips.
Innovation Solution
A laminated semiconductor package design featuring separate packages with insulating layers, wiring, and connecting sections, where a logic device is mounted on one package and a memory device on another, with a grid array configuration to support multiple pins and reduce thermal influence, allowing for thermal separation and increased connecting area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips including logic devices and memory devices are laminated in a single package, then space utilization is improved, but thermal radiation from logic devices degrades the reliability of memory devices
Solution Approach 1:
The invention divides the package into multiple independent packages, each containing semiconductor chips of the same type (logic devices in one package, memory devices in another). This segmentation prevents thermal radiation from logic devices from affecting memory devices, thereby maintaining system reliability while still achieving compact packaging through lamination of multiple packages.
2Reliability
If separate packages are used for logic devices and memory devices to reduce thermal influence, then reliability is improved, but device complexity and packaging difficulty increase
Solution Approach 1:
The invention uses a standardized package structure that can accommodate different types of semiconductor chips (logic devices, memory devices, etc.). Each package follows the same design template with identical mounting substrates, sealing structures, and connection interfaces, which simplifies manufacturing and assembly processes despite having multiple packages.
Solution Approach 2:
The invention laminates multiple standardized packages together in a nested configuration, where each package contains its own semiconductor chips and is sealed independently. This nested structure allows for compact arrangement while maintaining the thermal separation benefits of separate packages, reducing overall system complexity compared to attempting to integrate all chips in a single complex package.
3Quantity of substance
If flip-chip structure is used to mount semiconductor chips, then connection density is improved, but the area available for forming connecting sections between packages is reduced
Solution Approach 1:
The invention transitions from planar connection arrangements to three-dimensional vertical connections by forming connecting sections that extend through the thickness of the mounting substrate. This allows connection pins to be arranged in multiple layers and at various depths within the substrate, significantly increasing the effective connection area without increasing the surface footprint.
Solution Approach 2:
The invention introduces a mounting substrate as an intermediary layer between the semiconductor chip and the external environment. This substrate provides internal pathways (via holes, embedded conduits) that allow connection pins to traverse through the substrate thickness, enabling high-density connections while preserving surface area for package mounting and thermal management structures.
Data Source
AI summary
A laminated semiconductor package includes: a first package having: an insulating layer; a first semiconductor chip embedded in the insulating layer; a wiring connected to the first semiconductor chip; a first connecting section which is formed on a first face side of the insulating layer and connected to the wiring; and a second connecting section which is formed on a second face side of the insulating layer and connected to the wiring, the second face side being opposite to the first face side; and a second package having: a second semiconductor chip; and a third connecting section connected to the second semiconductor chip. In the laminated semiconductor chip, the first package and the second package are laminated one on the other, and the second connecting section and the third connecting section are connected to each other.