Laminated Image Sensor Circuit Structure for High-Speed Signal Readout
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Solution Overview
Problem
Existing image sensors face challenges in processing signals from photodiodes simultaneously at high speed due to limitations in wiring and substrate connections, leading to increased chip area and reduced aperture ratio.
Innovation Solution
The image sensor design incorporates multiple semiconductor substrates and wiring layers laminated in a specific order to facilitate efficient signal processing without increasing chip area, using through electrodes and connection layers to enable simultaneous signal transmission and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor substrates are laminated together with through electrodes to process signals from all photodiodes simultaneously, then signal processing speed and simultaneity are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The image sensor is divided into multiple independent semiconductor substrates (first substrate with photodiodes, second substrate with signal processing circuits, third substrate with memory). Each substrate performs a specific function and can be manufactured separately, then laminated together through through electrodes. This segmentation enables simultaneous signal processing across all photodiodes while managing complexity through modular design.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional lamination. By stacking multiple substrates vertically and connecting them through through electrodes, the design achieves high-speed simultaneous signal processing from all photodiodes without increasing chip area, resolving the contradiction between processing speed and device complexity.
2Productivity
If traditional wiring and substrate connections are used, then device complexity is reduced, but signal processing capability and aperture ratio are compromised
Solution Approach 1:
By moving from two-dimensional planar wiring to three-dimensional vertical stacking with through electrodes, the patent achieves enhanced signal processing capability without increasing chip area. The lamination structure allows multiple signal processing stages to occupy different vertical levels, maintaining a compact footprint while improving functionality.
3Productivity
If more wiring layers and connection structures are added to enable simultaneous signal processing, then signal transmission efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the signal processing function across multiple substrates, with each substrate containing specific wiring layers and circuits. This segmentation allows each substrate to be manufactured with standard precision requirements, then assembled through through electrode alignment. The modular approach avoids the need for extremely high manufacturing precision that would be required for complex monolithic structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for the simultaneous processing of signals from multiple photodiodes without increasing chip area, maintaining high aperture ratio and improving signal transmission efficiency.
Implementation Method 1
a first semiconductor substrate with a photoelectric conversion unit that photoelectrically converts incident light and generates charge
Data Source
AI summary
A first circuit layer including a first semiconductor substrate with photoelectric conversion unit that photoelectrically converts incident light and generates charge, and a first wiring layer with wiring that reads out signal based upon charge generated by the photoelectric conversion unit; second circuit layer including a second wiring layer with wiring connected to the wiring of the first wiring layer, and a second semiconductor substrate with a through electrode connected to the wiring of the second wiring layer; third circuit layer including a third semiconductor substrate with a through electrode connected to the through electrode of the second circuit layer, and third wiring layer with wiring connected to the through electrode of the third semiconductor substrate; and a fourth circuit layer including a fourth wiring layer with wiring connected to the wiring of the third wiring layer, and fourth semiconductor substrate connected to the wiring of the fourth wiring layer.