Laminated Power Module Terminals for Lower Inductance Packaging
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Solution Overview
Problem
The existing semiconductor devices face challenges in reducing the size while minimizing wiring inductance, as the arrangement of external terminals projecting from the sealing resin impedes a reduction in the overall size of power semiconductor modules.
Innovation Solution
A semiconductor device configuration with external terminals arranged in a laminated manner, where the positive and negative terminals project from one side surface and the intermediate terminal is exposed on the top surface, with insulating members interposed to reduce wiring inductance and achieve a smaller size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If external terminals are arranged in a stepped manner to be connected to external circuits, then the device can be connected to external circuits, but the entire size of the power semiconductor module increases
Solution Approach 1:
The patent transitions from a conventional stepped arrangement where terminals project from the same side surface to a laminated arrangement where terminals are distributed across different surfaces (side surface and top surface). This spatial redistribution in multiple dimensions allows terminals to be connected to external circuits while minimizing the projection distance and reducing the overall module size.
Solution Approach 2:
The patent embeds insulating members within the sealing resin structure, positioning them between the laminated terminals. This nested arrangement integrates insulation functionality into the existing structural volume without adding external protrusions, thereby maintaining compact dimensions while ensuring electrical isolation.
2Ease of operation
If external terminals project from the sealing resin, then the terminals can be connected to external circuits, but the distance and thickness of terminals increase wiring inductance
Solution Approach 1:
By distributing terminals across different surfaces (side and top) rather than having them all project from the same side, the patent reduces the effective projection distance of each terminal. This dimensional redistribution minimizes the loop area and reduces wiring inductance, improving electrical performance and reliability.
3Reliability
If insulating members are interposed between laminated terminals, then wiring inductance is reduced, but the device complexity increases
Solution Approach 1:
The patent integrates insulating members into the sealing resin structure, merging the insulation function with the existing encapsulation material. This consolidation approach reduces the need for separate insulation components and simplifies the manufacturing process, thereby reducing device complexity while maintaining the benefit of reduced wiring inductance.
Data Source
AI summary
A semiconductor device includes: an insulated circuit substrate; a semiconductor chip provided on a top surface side of the insulated circuit substrate; a sealing resin provided so as to seal the semiconductor chip; a first external terminal electrically connected to the semiconductor chip so as to be exposed on a first side surface of the sealing resin; a second external terminal electrically connected to the semiconductor chip and having a part opposed parallel to the first external terminal on an upper side of the first external terminal so as to be exposed on a top surface of the sealing resin; and a first insulating member interposed between the first external terminal and the second external terminal.