Landing Pad Barrier Layer for Node Contact Short-Circuit Prevention
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Solution Overview
Problem
In semiconductor devices, node contacts (NCs) often short-circuit during high-temperature wafer acceptance tests due to metal diffusion between the NCs and landing pads, leading to device failure and reduced yield.
Innovation Solution
A forming method and semiconductor device structure that includes forming a barrier layer on the exposed surfaces of the landing pads and node contacts to prevent metal diffusion, with the barrier layer being removable after electrical testing to avoid short-circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a barrier layer is formed on the landing pad and node contact surfaces, then metal diffusion is prevented and short-circuits are avoided, but the device structure becomes more complex and additional process steps are required
Solution Approach 1:
A barrier layer made of silicon nitride or silicon oxynitride is introduced as an intermediary material between the metal landing pad/node contact and the surrounding environment. This barrier layer acts as a mediator that prevents metal atom diffusion during high-temperature electrical tests while allowing the device to function normally. The barrier layer is temporarily present during testing and then removed, serving its protective function without permanently complicating the device structure.
Solution Approach 2:
The barrier layer is formed on the landing pad and node contact surfaces before the electrical test is performed. This preliminary protective action ensures that the metal surfaces are already protected against diffusion before the high-temperature testing begins, preventing short-circuits from occurring in the first place rather than addressing them after they form.
2Reliability
If the barrier layer is kept on the landing pad during electrical testing, then metal diffusion is prevented, but the electrical test cannot be properly performed due to insulation
Solution Approach 1:
The barrier layer is applied selectively only to the critical surfaces of the landing pad and node contacts where metal diffusion occurs, rather than covering the entire device. This localized application maintains the insulating protection exactly where needed to prevent diffusion, while leaving other areas accessible for proper electrical testing and signal transmission.
Solution Approach 2:
The barrier layer is formed in advance before electrical testing, establishing the protective configuration beforehand. After the electrical test is completed, the barrier layer is then removed. This sequence allows the barrier to provide protection during the critical diffusion-prone period without interfering with the electrical measurements that require direct metal contact.
3Measurement precision
If high-temperature electrical testing is performed on the semiconductor device, then device performance is verified, but metal diffusion causes short-circuits between node contacts
Solution Approach 1:
The barrier layer serves as a protective intermediary that blocks the diffusion pathway for metal atoms during high-temperature electrical testing. By introducing this intermediate protective layer, the harmful thermal diffusion effect is prevented while allowing the beneficial electrical performance verification to proceed uninterrupted at the required high temperatures.
Solution Approach 2:
The barrier layer is applied in advance to counteract the harmful effect of metal diffusion before the high-temperature testing begins. This preliminary protective measure creates resistance against the anticipated diffusion harm, allowing the electrical test to be performed at high temperatures without the feared short-circuit consequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The barrier layer effectively prevents conductive metal atoms from diffusing and causing short-circuits, thereby improving the performance and yield of semiconductor devices by ensuring reliable electrical testing and preventing damage during high-temperature tests.
Implementation Method 1
prevent the metal diffusion of the landing pad and the node contact during the electrical test
Data Source
AI summary
The present disclosure relates to a semiconductor device and a forming method thereof. The forming method includes: providing a substrate; forming node contacts inside the substrate; forming landing pads on an upper surface of the substrate, where the landing pad is in contact with the node contact; forming a barrier layer on exposed surfaces of the landing pads and the node contacts; and after performing an electrical test on the semiconductor device on which the barrier layer is formed, removing the barrier layer on an upper surface of the landing pads.