Landing Pad and Differentiated Interconnects for Lower Parasitic Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices integrate, the area occupied by capacitors decreases, leading to reduced sensing margin, and existing methods to lower parasitic capacitance are limited by the high dielectric constant of dielectric materials.
Innovation Solution
A semiconductor device design with differentiated metal wires, where the thickness of the first metal wire is smaller than the second, reducing parasitic capacitance and maintaining low resistance, achieved through a fabrication method involving a capping layer and etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If metal wires of different heights are formed in a peripheral circuit region, then parasitic capacitance is reduced, but device complexity increases
Solution Approach 1:
The patent applies local quality by forming metal wires of different thicknesses in different regions of the peripheral circuit. Specifically, a first metal wire with a first thickness is formed in a first peripheral circuit region, while a second metal wire with a second thickness (greater than the first) is formed in a second peripheral circuit region. This localized differentiation reduces parasitic capacitance in specific areas without unnecessarily complicating the entire device structure.
Solution Approach 2:
The patent segments the peripheral circuit region into multiple regions with different metal wire thicknesses. The peripheral circuit region is divided into a first peripheral circuit region containing a first metal wire and a second peripheral circuit region containing a second metal wire. This segmentation allows for optimized capacitance management in different functional areas while maintaining overall device performance.
2Object-generated harmful factors
If the thickness of metal wires is reduced to lower parasitic capacitance, then sensing margin is improved, but electrical resistance increases
Solution Approach 1:
The patent implements local quality by assigning different metal wire thicknesses to different functional regions. In the first peripheral circuit region, a thinner first metal wire reduces parasitic capacitance to improve sensing margin. In the second peripheral circuit region, a thicker second metal wire maintains low electrical resistance for reliable signal transmission. This localized approach allows simultaneous optimization of both capacitance and resistance characteristics.
Solution Approach 2:
The patent segments the device into regions with different electrical performance requirements. The first peripheral circuit region uses thinner metal wires optimized for low capacitance applications, while the second peripheral circuit region uses thicker metal wires optimized for low resistance applications. This segmentation enables each region to be optimized for its specific functional requirements without compromising overall device performance.
Data Source
AI summary
A semiconductor device includes a substrate including a memory cell region and a peripheral circuit region, the peripheral circuit region including a first peripheral circuit region including a first transistor and a second peripheral circuit region including a second transistor; a storage node contact plug positioned in an upper portion of the substrate in the memory cell region; a landing pad over the storage node contact plug; a first metal wire coupled to the first transistor; and a second metal wire coupled to the second transistor, wherein a thickness of the landing pad and a thickness of the first metal wire are smaller than a thickness of the second metal wire.