Landing Pad Sidewall Geometry for Etching Control in Semiconductor Staircase Structures
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Solution Overview
Problem
The miniaturization of semiconductor structures leads to difficulties in forming interconnections due to very thin conductive films, resulting in frequent over-etching issues and yield loss.
Innovation Solution
A semiconductor structure with a staircase design featuring a landing pad, where the landing pad has a unique sidewall configuration and lateral gap distances that help control the etching process, including a first pad sidewall with a concave portion facing toward the second stair layer, allowing for precise formation of interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the conductive film thickness is reduced to enable miniaturization, then the semiconductor structure scaling is achieved, but the etching process control becomes difficult and over-etching occurs frequently
Solution Approach 1:
The patent applies preliminary action by forming a landing pad structure with increased conductive film thickness in advance, before the interconnection etching process. This pre-formed thicker conductive layer serves as a buffer that prevents over-etching of the underlying thin conductive films, thereby solving the etching control difficulty while maintaining the miniaturized structure dimensions.
Solution Approach 2:
The patent implements local quality by creating a landing pad with locally increased conductive film thickness only at specific critical locations where interconnections are formed. The rest of the conductive film maintains its thin profile for miniaturization. This localized thickening provides etching protection precisely where needed without compromising the overall scaled-down structure.
2Volume of moving object
If the conductive film thickness is reduced for miniaturization, then device scaling is achieved, but yield loss increases due to over-etching
Solution Approach 1:
The landing pad is formed in advance with a thicker conductive film that acts as an etching stop layer. This preliminary structural preparation prevents over-etching during subsequent interconnection formation processes, thereby eliminating the cause of yield loss while maintaining the miniaturized device dimensions.
3Manufacturing precision
If a thicker conductive film is added at the landing area, then etching process control is improved and over-etching is prevented, but the device complexity increases
Solution Approach 1:
The patent reduces device complexity by implementing the thicker conductive film only locally at the landing pad areas where etching control is critical. The majority of the conductive film structure remains thin and simple. This localized approach provides the necessary etching protection without significantly increasing the overall device structural complexity.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a staircase structure including a first stair layer and a second stair layer on the first stair layer. The first stair layer comprises a first conductive film. The semiconductor structure includes a landing pad disposed on the first conductive film. The landing pad has a first pad sidewall facing toward the second stair layer, a first lateral gap distance between an upper portion of the first pad sidewall and the second stair layer is smaller than a second lateral gap distance between a lower portion of the first pad sidewall and the second stair layer.