Landing Plug Etch-Back Process for Height Uniformity Control
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Solution Overview
Problem
The conventional etch-back process for forming landing plugs in semiconductor devices results in a height difference between upper portions, making it difficult to control the etch amount and deposition thickness, thereby decreasing the yield of semiconductor memory devices.
Innovation Solution
A method involving a breakthrough process, a first main etch process, and an over-etch process is used to minimize the height difference between adjacent landing plugs, utilizing isotropic and anisotropic etch processes with specific gas and power settings to control the etch rate and deposition thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a conventional anisotropic etch-back process is used to form landing plugs, then the contact hole area is reduced, but a height difference between upper portions of adjacent landing plugs occurs
Solution Approach 1:
The etch-back process is divided into multiple sequential steps (breakthrough process, first main etch process, second main etch process, and over-etch process) with different etch gases and parameters. Each step targets specific removal requirements, collectively achieving both area reduction and height uniformity that cannot be obtained by a single conventional etch step.
Solution Approach 2:
The patent changes multiple process parameters including etch gas composition (switching between CF4, C2F6, and other gases), pressure conditions, and power settings between different etch steps. These parameter changes allow optimization of etch rate and selectivity at each stage to control landing plug height uniformity while maintaining reduced contact hole area.
2Speed
If chlorine (Cl2) gas is used in the etch-back process for higher etch rate, then the etching speed increases, but the height difference between landing plugs becomes even larger
Solution Approach 1:
The patent replaces chlorine (Cl2) gas with alternative etch gases such as CF4 and C2F6 that provide different etch characteristics. These gas changes modify the etch rate and selectivity to reduce height differences between landing plugs while maintaining sufficient etching speed for process efficiency.
Solution Approach 2:
Instead of using a single high-rate chlorine etch step that causes height differences, the patent segments the etching into multiple steps with different gases. The first step may use higher etch rate gases, while subsequent steps use gases with better uniformity characteristics, collectively achieving both speed and precision.
3Device complexity
If a single etch-back process is used, then the process complexity is low, but the control over etch amount and deposition thickness is poor
Solution Approach 1:
The patent divides the etch-back process into four distinct sequential steps, each with specific process parameters and objectives. This segmentation enables precise control over etch amount and deposition thickness at each stage, achieving manufacturing precision that would be impossible with a single undifferentiated etch step.
Solution Approach 2:
The breakthrough process serves as a preliminary step that removes excess conductive material and prepares the surface for subsequent main etch processes. This preliminary action ensures that the following steps can achieve precise depth control and uniform landing plug formation, improving overall manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively minimizes the height difference between the upper portions of adjacent landing plugs, improving the control over the etch amount and deposition thickness, thereby enhancing the yield of semiconductor memory devices.
Implementation Method 1
performing a breakthrough process, a first main etch process, a second main etch process, and an over-etch process
Data Source
AI summary
A method for fabricating a semiconductor device includes forming an interlayer dielectric layer having a plurality of contact holes over a substrate, forming a conductive layer by filling the contact holes to cover the interlayer dielectric layer, performing a first main etch process to partially etch the conductive layer to form a first conductive layer, performing a second main etch process to etch the first conductive layer using an etch gas having a slower etch rate with respect to the first conductive layer than an etch gas used in the first main etch process until an upper surface of the interlayer dielectric layer is exposed to form a second conductive layer, and performing an over-etch process to etch a certain portion of the second conductive layer, and at the same time, to etch a certain portion of the interlayer dielectric layer to form a landing plug.