Lane-Based FPGA Logic Circuit for Higher Logic Density
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Solution Overview
Problem
Conventional eFPGAs face challenges in improving logic density due to the use of full crossbar connections and the requirement for numerous component memories, which limits the implementation of logic cells.
Innovation Solution
A programmable logic circuit with a new wiring architecture that maps nodes on a netlist hierarchy, reducing the need for full crossbar connections by using lanes with programmable selector circuits and flip-flops, thereby optimizing signal flow and minimizing the number of component memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If full crossbar connections are used to connect all logic cell outputs to all logic cell inputs, then high wiring flexibility is achieved, but the number of multiplexers and component memories increases significantly
Solution Approach 1:
The patent segments the full crossbar connection into multiple lanes, where each lane contains a subset of logic cells. This segmentation reduces the wiring complexity within each lane while maintaining overall system flexibility through inter-lane connections. The segmentation principle directly addresses the contradiction by dividing the large-scale crossbar into manageable units with reduced multiplexer requirements.
Solution Approach 2:
The patent introduces a new dimensional organization by arranging logic cells in sequential lanes rather than using a traditional two-dimensional grid. This lane-based arrangement adds a temporal dimension to the wiring architecture, allowing signals to flow sequentially through lanes while reducing the need for full crossbar connections. This dimensional change resolves the contradiction by providing flexibility through sequential access rather than simultaneous full crossbar connectivity.
2Adaptability or versatility
If FFs are added to all outputs of M-output N-input LUTs to enable programmable logic functionality, then logic versatility is improved, but the area of logic cells increases several times
Solution Approach 1:
The patent makes the FF circuit universal by enabling it to serve multiple functions: it acts as a feedback register for the current lane, provides output registration, and can be configured to connect to different lanes. This multi-functionality eliminates the need for separate FFs at each LUT output, reducing the overall logic cell area while maintaining full programmable logic functionality. The universal FF resolves the contradiction by providing versatility through configuration rather than through proliferation of components.
3Quantity of substance
If SRAMs are used for LUT memories in standard FPGAs, then logic density is improved, but the design becomes difficult to implement in ASICs
Solution Approach 1:
The patent copies the functional behavior of SRAM-based LUTs using FF-based structures. Instead of using actual SRAM cells, the invention creates equivalent logic functionality using FFs configured as lookup tables with programmable next-state logic. This copying approach maintains the logic density benefits of SRAM-based designs while adapting them to be manufacturable in ASIC processes, resolving the contradiction between density and manufacturability.
Data Source
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AI summary
Conventional FPGAs have a problem of improving implemented logic density, and there is a need for a programmable logic circuit with a new structure capable of solving this problem. There is provided a programmable logic circuit (26), comprising a plurality of lanes (27) sequentially connected in the programmable logic circuit in a direction of flow of input signals of this programmable logic circuit, wherein each of the plurality of lanes has one or more logic cells (27), inputs input signals (Ia-Id) into the lane to each logic cell via a program-controllable input-side selector circuit, and outputs output signals (Oa-Oc) from the each logic cell as input signals into a next sequential lane connected to this lane or/and outputs the output signals as output signals of this programmable logic circuit.